AT80C51RD2-3CSUM Atmel, AT80C51RD2-3CSUM Datasheet - Page 10

• Manufacturer Part Number: AT80C51RD2-3CSUM
• Description: IC, 8BIT MCU, 80C51, 40MHZ, DIP-40
• Manufacturer: Atmel

Specifications of AT80C51RD2-3CSUM

• Controller Family/series: 80C51
• No. Of I/o's: 32
• Ram Memory Size: 1280Byte
• Cpu Speed: 40MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 5
• Digital Ic Case Style: DIP
• Core Size: 8 Bit
• Rohs Compliant: Yes
• Processor Series: AT80x
• Core: 8051
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Data Ram Size: 1280 B
• Interface Type: UART, SPI
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Package / Case: PDIL-40
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• Cpu Family: AT80
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 40MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 1.25KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 40
• Package Type: PDIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 6-2.
10
AT80C51RD2
XTAL1
XTAL1:2
X2 Bit
CPU Block
Mode Switching Waveforms
STD Mode
The X2 bit in the CKCON0 register (see Table 6-1) allows to switch from 12 clock periods per
instruction to 6 clock periods and vice versa. At reset, the speed is set according to X2 bit of
Hardware Config Byte (HCB). By default, Standard mode is activated. Setting the X2 bit acti-
vates the X2 feature (X2 mode).
The T0X2, T1X2, T2X2, UARTX2, PCAX2 and WDX2 bits in the CKCON0 register
allow to switch from standard peripheral speed (12 clock periods per peripheral clock cycle) to
fast peripheral speed (6 clock periods per peripheral clock cycle). These bits are active only in
X2 mode.
Table 6-1.
CKCON0 - Clock Control Register (8Fh)
Number
Bit
7
6
7
-
Mnemonic
CKCON0 Register
WDX2
WDX2
Bit
6
-
Description
Reserved
Do not set this bit.
Watchdog clock (This control bit is validated when the CPU clock X2 is set; when X2
is low, this bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
PCAX2
5
F
OSC
X2 Mode
SIX2
4
T2X2
3
T1X2
2
STD Mode
T0X2
1
4113D–8051–01/09
(Table
X2
0
6-1)