ADSP-BF538BBCZ-5F4 Analog Devices Inc, ADSP-BF538BBCZ-5F4 Datasheet - Page 28

• Manufacturer Part Number: ADSP-BF538BBCZ-5F4
• Description: IC, FLOAT-PT DSP, 16BIT, 533MHZ, BGA-316
• Manufacturer: Analog Devices Inc
• Series: Blackfinr
• Type: Fixed Pointr

Specifications of ADSP-BF538BBCZ-5F4

• No. Of Bits: 16 Bit
• Frequency: 533MHz
• Supply Voltage: 1.25V
• Embedded Interface Type: CAN, I2C, PPI, SPI, TWI, UART
• No. Of I/o's: 54
• Flash Memory Size: 512KB
• Interface: CAN, SPI, SSP, TWI, UART
• Clock Rate: 533MHz
• Non-volatile Memory: FLASH (512 kB)
• On-chip Ram: 148kB
• Voltage - I/o: 3.00V, 3.30V
• Voltage - Core: 1.25V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 316-CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADZS-BFAUDIO-EZEXT - BOARD EVAL AUDIO BLACKFIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADSP-BF538/ADSP-BF538F
Asynchronous Memory Read Cycle Timing
Table 18
on Page 29
tions for synchronous and for asynchronous ARDY.
Table 18. Asynchronous Memory Read Cycle Timing with Synchronous ARDY
1
Parameter
Timing Requirements
t
t
t
t
t
t
Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.
SDAT
HDAT
SARDY
HARDY
DO
HO
CLKOUT
ADDR19–1
AMSx
ABE1–0
AOE
ARE
ARDY
DATA15–0
and
describe asynchronous memory read cycle opera-
Table 19 on Page 29
DATA15–0 Setup Before CLKOUT
DATA15–0 Hold After CLKOUT
ARDY Setup Before the Falling Edge of CLKOUT
ARDY Hold After the Falling Edge of CLKOUT
Output Delay After CLKOUT
Output Hold After CLKOUT
2 CYCLES
SETUP
t
DO
and
Figure 11. Asynchronous Memory Read Cycle Timing with Synchronous ARDY
Figure 11
1
1
and
PROGRAMMED READ ACCESS
t
DO
Rev. A | Page 28 of 56 | January 2008
Figure 12
4 CYCLES
t
SARDY
BE, ADDRESS
t
HARDY
ACCESS EXTENDED
3 CYCLES
t
SARDY
Min
2.1
0.8
4.0
0.0
0.8
t
t
HO
SDAT
READ
t
HARDY
1 CYCLE
HOLD
Max
6.0
t
HDAT
t
HO
Unit
ns
ns
ns
ns
ns
ns