ADSP-BF538BBCZ-5F4 Analog Devices Inc, ADSP-BF538BBCZ-5F4 Datasheet - Page 12

• Manufacturer Part Number: ADSP-BF538BBCZ-5F4
• Description: IC, FLOAT-PT DSP, 16BIT, 533MHZ, BGA-316
• Manufacturer: Analog Devices Inc
• Series: Blackfinr
• Type: Fixed Pointr

Specifications of ADSP-BF538BBCZ-5F4

• No. Of Bits: 16 Bit
• Frequency: 533MHz
• Supply Voltage: 1.25V
• Embedded Interface Type: CAN, I2C, PPI, SPI, TWI, UART
• No. Of I/o's: 54
• Flash Memory Size: 512KB
• Interface: CAN, SPI, SSP, TWI, UART
• Clock Rate: 533MHz
• Non-volatile Memory: FLASH (512 kB)
• On-chip Ram: 148kB
• Voltage - I/o: 3.00V, 3.30V
• Voltage - Core: 1.25V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 316-CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADZS-BFAUDIO-EZEXT - BOARD EVAL AUDIO BLACKFIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADSP-BF538/ADSP-BF538F
Table 4. GPIO Ports
1
PARALLEL PERIPHERAL INTERFACE
The ADSP-BF538/ADSP-BF538F processors provide a parallel
peripheral interface (PPI) that can connect directly to parallel
A/D and D/A converters, video encoders and decoders, and
other general-purpose peripherals. The PPI consists of a dedi-
cated input clock pin, up to 3 frame synchronization pins, and
up to 16 data pins. The input clock supports parallel data rates at
up to f
figured as either inputs or outputs.
The PPI supports a variety of general-purpose and ITU-R 656
modes of operation. In general-purpose mode, the PPI provides
half-duplex, bi-directional data transfer with up to 16 bits of
data. Up to 3 frame synchronization signals are also provided.
In ITU-R 656 mode, the PPI provides half-duplex, bi-direc-
tional transfer of 8- or 10-bit video data. Additionally, on-chip
decode of embedded start-of-line (SOL) and start-of-field (SOF)
preamble packets is supported.
Peripheral
PPI
SPORT2
SPORT3
SPI0
SPI1
SPI2
UART1
UART2
CAN
GPIO
These pins are GPIO only and cannot be reconfigured through software. PC1
and PC4 are open-drain when configured as GPIO outputs.
• GPIO pin interrupt sensitivity registers – The two GPIO
interrupt function. PFx pins defined as inputs can be con-
figured to generate hardware interrupts, while output PFx
pins can be triggered by software interrupts.
pin interrupt sensitivity registers specify whether individ-
ual PFx pins are level- or edge-sensitive and specify—if
edge-sensitive—whether just the rising edge or both the ris-
ing and falling edges of the signal are significant. One
register selects the type of sensitivity, and one register
selects which edges are significant for edge-sensitivity.
SCLK
/2 MHz, and the synchronization signals can be con-
Alternate GPIO Port Function
GPIO Port F15–3
GPIO Port E7–0
GPIO Port E15–8
GPIO Port F7–0
GPIO Port D4–0
GPIO Port D9–5
GPIO Port D11–10
GPIO Port D13–12
GPIO Port C1–0
GPIO Port C9–4
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Rev. A | Page 12 of 56 | January 2008
General-Purpose Mode Descriptions
The general-purpose modes of the PPI are intended to suit a
wide variety of data capture and transmission applications.
Three distinct submodes are supported:
Input Mode
Input mode is intended for ADC applications, as well as video
communication with hardware signaling. In its simplest form,
PPI_FS1 is an external frame sync input that controls when to
read data. The PPI_DELAY MMR allows for a delay (in
PPI_CLK cycles) between reception of this frame sync and the
initiation of data reads. The number of input data samples is
user programmable and defined by the contents of the
PPI_COUNT register. The PPI supports 8-bit, and 10-bit
through 16-bit data, and are programmable in the
PPI_CONTROL register.
Frame Capture Mode
Frame capture mode allows the video source(s) to act as a slave
(e.g., for frame capture). The ADSP-BF538/ADSP-BF538F pro-
cessors control when to read from the video source(s). PPI_FS1
is an HSYNC output and PPI_FS2 is a VSYNC output.
Output Mode
Output mode is used for transmitting video or other data with
up to three output frame syncs. Typically, a single frame sync is
appropriate for data converter applications, whereas two or
three frame syncs could be used for sending video with hard-
ware signaling.
ITU-R 656 Mode Descriptions
The ITU-R 656 modes of the PPI are intended to suit a wide
variety of video capture, processing, and transmission applica-
tions. Three distinct submodes are supported:
Active Video Only Mode
Active video only mode is used when only the active video por-
tion of a field is of interest and not any of the blanking intervals.
The PPI does not read in any data between the end of active
video (EAV) and start of active video (SAV) preamble symbols,
or any data present during the vertical blanking intervals. In this
mode, the control byte sequences are not stored to memory;
they are filtered by the PPI. After synchronizing to the start of
Field 1, the PPI ignores incoming samples until it sees an SAV
code. The user specifies the number of active video lines per
frame (in PPI_COUNT register).
• Input mode – frame syncs and data are inputs into the PPI.
• Frame capture mode – frame syncs are outputs from the
• Output mode – frame syncs and data are outputs from the
• Active video only mode
• Vertical blanking only mode
• Entire field mode
PPI, but data are inputs.
PPI.