ADSP-BF538BBCZ-5F4 Analog Devices Inc, ADSP-BF538BBCZ-5F4 Datasheet - Page 19

• Manufacturer Part Number: ADSP-BF538BBCZ-5F4
• Description: IC, FLOAT-PT DSP, 16BIT, 533MHZ, BGA-316
• Manufacturer: Analog Devices Inc
• Series: Blackfinr
• Type: Fixed Pointr

Specifications of ADSP-BF538BBCZ-5F4

• No. Of Bits: 16 Bit
• Frequency: 533MHz
• Supply Voltage: 1.25V
• Embedded Interface Type: CAN, I2C, PPI, SPI, TWI, UART
• No. Of I/o's: 54
• Flash Memory Size: 512KB
• Interface: CAN, SPI, SSP, TWI, UART
• Clock Rate: 533MHz
• Non-volatile Memory: FLASH (512 kB)
• On-chip Ram: 148kB
• Voltage - I/o: 3.00V, 3.30V
• Voltage - Core: 1.25V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 316-CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADZS-BFAUDIO-EZEXT - BOARD EVAL AUDIO BLACKFIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIN DESCRIPTIONS
The ADSP-BF538/ADSP-BF538F processors pin definitions are
listed in
All pins are three-stated during and immediately after reset,
except the memory interface, asynchronous memory control,
and synchronous memory control pins, which are driven high.
If BR is active, then the memory pins are also three-stated. All
Table 10. Pin Descriptions
Pin Name
Memory Interface
ADDR19–1
DATA15–0
ABE1–0/SDQM1–0
BR
BG
BGH
Asynchronous Memory Control
AMS3–0
ARDY
AOE
ARE
AWE
Flash Control
FCE
FRESET
Synchronous Memory Control
SRAS
SCAS
SWE
SCKE
CLKOUT
SA10
SMS
Timers
TMR0
TMR1/PPI_FS1
TMR2/PPI_FS2
Table
10.
I/O
O
I/O
O
I
O
O
O
I
O
O
O
I
I
O
O
O
O
O
O
O
I/O
I/O
I/O
Address Bus for Async/Sync Access
Data Bus for Async/Sync Access
Flash Enable (This pin should be left unconnected or pulled low for the
Clock Output
Function
Byte Enables/Data Masks for Async/Sync Access
Bus Request (This pin should be pulled high when not used.)
Bus Grant
Bus Grant Hang
Bank Select
Hardware Ready Control (This pin should always be pulled low when not
used.)
Output Enable
Read Enable
Write Enable
ADSP-BF538.)
Flash Reset (This pin should be left unconnected or pulled low for the
ADSP-BF538.)
Row Address Strobe
Column Address Strobe
Write Enable
Clock Enable
A10 Pin
Bank Select
Timer 0
Timer 1/PPI Frame Sync1
Timer 2/PPI Frame Sync2
Rev. A | Page 19 of 56 | January 2008
unused I/O pins have their input buffers disabled with the
exception of the pins that need pull-ups or pull-downs, as noted
in the table.
In order to maintain maximum functionality and reduce pack-
age size and pin count, some pins have dual, multiplexed
functionality. In cases where pin functionality is reconfigurable,
the default state is shown in plain text, while alternate function-
ality is shown in italics.
ADSP-BF538/ADSP-BF538F
Driver Type
A
A
A
A
A
A
A
A
A
A
A
A
B
A
A
C
C
C
A
1