DSPIC30F5011-20I/PTG Microchip Technology, DSPIC30F5011-20I/PTG Datasheet - Page 33

• Manufacturer Part Number: DSPIC30F5011-20I/PTG
• Description: IC, DSC, 16BIT, 66KB, 40MHZ 5.5V TQFP-64
• Manufacturer: Microchip Technology
• Series: DsPIC30Fr

Specifications of DSPIC30F5011-20I/PTG

• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 52
• Flash Memory Size: 66KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

All byte loads into any W register are loaded into the
LSB. The MSB is not modified.
A sign-extend (SE) instruction is provided to allow
users to translate 8-bit signed data to 16-bit signed
values. Alternatively, for 16-bit unsigned data, users
can clear the MSB of any W register by executing a
zero-extend (ZE) instruction on the appropriate
address.
Although most instructions are capable of operating on
word or byte data sizes, it should be noted that some
instructions, including the DSP instructions, operate
only on words.
3.2.5
An 8 Kbyte ‘near’ data space is reserved in X address
memory space between 0x0000 and 0x1FFF, which is
directly addressable via a 13-bit absolute address field
within all memory direct instructions. The remaining X
address space and all of the Y address space is
addressable indirectly. Additionally, the whole of X data
space is addressable using MOV instructions, which
support memory direct addressing with a 16-bit
address field.
3.2.6
The dsPIC DSC devices contain a software stack. W15
is used as the Stack Pointer.
The Stack Pointer always points to the first available
free word and grows from lower addresses towards
higher addresses. It pre-decrements for stack pops
and post-increments for stack pushes as shown in
Figure 3-9. Note that for a PC push during any CALL
instruction, the MSB of the PC is zero-extended before
the push, ensuring that the MSB is always clear.
© 2008 Microchip Technology Inc.
Note:
NEAR DATA SPACE
SOFTWARE STACK
A PC push during exception processing
will concatenate the SRL register to the
MSB of the PC prior to the push.
There is a Stack Pointer Limit register (SPLIM)
associated
uninitialized at Reset. As is the case for the Stack
Pointer, SPLIM<0> is forced to ‘0’ because all stack
operations must be word aligned. Whenever an
Effective Address (EA) is generated using W15 as a
source or destination pointer, the address thus
generated is compared with the value in SPLIM. If the
contents of the Stack Pointer (W15) and the SPLIM reg-
ister are equal and a push operation is performed, a
Stack Error Trap will not occur. The Stack Error Trap will
occur on a subsequent push operation. Thus, for exam-
ple, if it is desirable to cause a Stack Error Trap when
the stack grows beyond address 0x2000 in RAM,
initialize the SPLIM with the value 0x1FFE.
Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0x0800, thus preventing the stack from
interfering with the Special Function Register (SFR)
space.
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
FIGURE 3-9:
3.2.7
The dsPIC30F5011/5013 devices support data RAM
protection features which enable segments of RAM to
be protected when used in conjunction with Boot and
Secure Code Segment Security. BSRAM (Secure RAM
segment for BS) is accessible only from the Boot
Segment Flash code when enabled. SSRAM (Secure
RAM segment for RAM) is accessible only from the
Secure Segment Flash code when enabled. See Table
3-3 for the BSRAM and SSRAM SFRs.
0x0000
dsPIC30F5011/5013
15
000000000
DATA RAM PROTECTION FEATURE
with
<Free Word>
PC<15:0>
the
PC<22:16>
CALL STACK FRAME
Stack
0
Pointer.
POP : [--W15]
PUSH : [W15++]
W15 (before CALL)
W15 (after CALL)
DS70116H-page 33
SPLIM
is