DSPIC30F5011-20I/PTG Microchip Technology, DSPIC30F5011-20I/PTG Datasheet - Page 214

• Manufacturer Part Number: DSPIC30F5011-20I/PTG
• Description: IC, DSC, 16BIT, 66KB, 40MHZ 5.5V TQFP-64
• Manufacturer: Microchip Technology
• Series: DsPIC30Fr

Specifications of DSPIC30F5011-20I/PTG

• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 52
• Flash Memory Size: 66KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

dsPIC30F5011/5013
Data Address Space ........................................................... 29
Data Converter Interface (DCI) Module ............................ 119
Data EEPROM Memory ...................................................... 55
DC Characteristics ............................................................ 167
DCI Module
DS70116H-page 214
Data Space Write Saturation ...................................... 23
Overflow and Saturation ............................................. 21
Round Logic ................................................................ 22
Write Back................................................................... 22
Alignment .................................................................... 32
Alignment (Figure) ...................................................... 32
Effect of Invalid Memory Accesses (Table)................. 32
MCU and DSP (MAC Class) Instructions Example..... 31
Memory Map ......................................................... 29, 30
Near Data Space ........................................................ 33
Software Stack ............................................................ 33
Spaces ........................................................................ 32
Width ........................................................................... 32
Erasing ........................................................................ 56
Erasing, Block ............................................................. 56
Erasing, Word ............................................................. 56
Protection Against Spurious Write .............................. 59
Reading....................................................................... 55
Write Verify ................................................................. 59
Writing ......................................................................... 57
Writing, Block .............................................................. 58
Writing, Word .............................................................. 57
BOR .......................................................................... 175
Brown-out Reset ....................................................... 174
I/O Pin Output Specifications .................................... 173
Idle Current (I
Low-Voltage Detect................................................... 173
LVDL ......................................................................... 174
Operating Current (I
Power-Down Current (I
Program and EEPROM............................................. 175
Temperature and Voltage Specifications .................. 168
Bit Clock Generator................................................... 123
Buffer Alignment with Data Frames .......................... 125
Buffer Control ............................................................ 119
Buffer Data Alignment ............................................... 119
Buffer Length Control ................................................ 125
COFS Pin.................................................................. 119
CSCK Pin.................................................................. 119
CSDI Pin ................................................................... 119
CSDO Mode Bit ........................................................ 126
CSDO Pin ................................................................. 119
Data Justification Control Bit ..................................... 124
Device Frequencies for Common Codec CSCK
Frequencies (Table) .................................................. 123
Digital Loopback Mode ............................................. 126
Enable....................................................................... 121
Frame Sync Generator ............................................. 121
Frame Sync Mode Control Bits ................................. 121
I/O Pins ..................................................................... 119
Interrupts ................................................................... 126
Introduction ............................................................... 119
Master Frame Sync Operation .................................. 121
Operation .................................................................. 121
Operation During CPU Idle Mode ............................. 126
Operation During CPU Sleep Mode .......................... 126
Receive Slot Enable Bits........................................... 124
Receive Status Bits ................................................... 125
Register Map............................................................. 128
Sample Clock Edge Control Bit................................. 124
IDLE
) .................................................... 170
DD
)............................................. 169
PD
) ........................................ 171
Development Support ....................................................... 163
Device Configuration
Device Configuration Registers
Device Overview................................................................... 9
Disabling the UART .......................................................... 103
Divide Support .................................................................... 18
DSP Engine ........................................................................ 19
Dual Output Compare Match Mode .................................... 86
E
Electrical Characteristics .................................................. 167
Enabling and Setting Up UART
Enabling the UART ........................................................... 103
Equations
Errata .................................................................................... 7
Exception Sequence
External Clock Timing Characteristics
External Clock Timing Requirements ............................... 177
External Interrupt Requests ................................................ 41
F
Fast Context Saving ........................................................... 41
Flash Program Memory ...................................................... 49
I
I/O Ports.............................................................................. 61
Slave Frame Sync Operation.................................... 122
Slot Enable Bits Operation with Frame Sync............ 124
Slot Status Bits ......................................................... 126
Synchronous Data Transfers .................................... 124
Timing Characteristics
Timing Requirements
Transmit Slot Enable Bits ......................................... 124
Transmit Status Bits.................................................. 125
Transmit/Receive Shift Register ............................... 119
Underflow Mode Control Bit...................................... 126
Word Size Selection Bits .......................................... 121
Register Map ............................................................ 153
FBORPOR ................................................................ 151
FBS........................................................................... 151
FGS .......................................................................... 151
FOSC........................................................................ 151
FSS........................................................................... 151
FWDT ....................................................................... 151
Instructions (Table) ..................................................... 18
Multiplier ..................................................................... 21
Continuous Pulse Mode.............................................. 86
Single Pulse Mode...................................................... 86
AC............................................................................. 176
DC ............................................................................ 167
Setting Up Data, Parity and Stop Bit Selections ....... 103
ADC Conversion Clock ............................................. 131
Baud Rate................................................................. 105
Bit Clock Frequency.................................................. 123
COFSG Period.......................................................... 121
Serial Clock Rate ........................................................ 98
Time Quantum for Clock Generation ........................ 115
Trap Sources .............................................................. 39
Type A, B and C Timer ............................................. 184
Type A Timer ............................................................ 184
Type B Timer ............................................................ 185
Type C Timer ............................................................ 185
AC-Link Mode................................................... 191
Multichannel, I
AC-Link Mode................................................... 191
Multichannel, I
2
2
S Modes................................... 189
S Modes................................... 190
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