DSPIC30F5011-20I/PTG Microchip Technology, DSPIC30F5011-20I/PTG Datasheet - Page 29

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DSPIC30F5011-20I/PTG

Manufacturer Part Number
DSPIC30F5011-20I/PTG
Description
IC, DSC, 16BIT, 66KB, 40MHZ 5.5V TQFP-64
Manufacturer
Microchip Technology
Series
DsPIC30Fr
Datasheet

Specifications of DSPIC30F5011-20I/PTG

Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
CAN, I2C, SPI, UART
No. Of I/o's
52
Flash Memory Size
66KB
Supply Voltage Range
2.5V To 5.5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
FIGURE 3-5:
3.2
The core has two data spaces. The data spaces can be
considered
instructions), or as one unified linear address range (for
MCU instructions). The data spaces are accessed
using two Address Generation Units (AGUs) and
separate data paths.
© 2008 Microchip Technology Inc.
Data
Space
EA
Note:
Upper Half of Data
Space is Mapped
into Program Space
BSET
MOV
MOV
MOV
Data Address Space
16
EA<15> = 0
EA<15> = 1
either
CORCON,#2
#0x01, W0
W0, PSVPAG
0x8000, W0
PSVPAG is an 8-bit register, containing bits <22:15> of the program space address (i.e., it defines
the page in program space to which the upper half of data space is being mapped).
DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION
separate
15
15
; PSV bit set
; Set PSVPAG register
; Access program memory location
; using a data space access
Data Space
(for
some
0x0000
0x8000
0xFFFF
15
DSP
Concatenation
Address
PSVPAG
0x01
3.2.1
The data space memory is split into two blocks, X and
Y data space. A key element of this architecture is that
Y space is a subset of X space, and is fully contained
within X space. In order to provide an apparent linear
addressing space, X and Y spaces have contiguous
addresses.
8
dsPIC30F5011/5013
(1)
23
23
DATA SPACE MEMORY MAP
Program Space
15
Data Read
DS70116H-page 29
0
0x000100
0x008000
0x017FFF

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