DSPIC30F5011-20I/PTG Microchip Technology, DSPIC30F5011-20I/PTG Datasheet - Page 135

• Manufacturer Part Number: DSPIC30F5011-20I/PTG
• Description: IC, DSC, 16BIT, 66KB, 40MHZ 5.5V TQFP-64
• Manufacturer: Microchip Technology
• Series: DsPIC30Fr

Specifications of DSPIC30F5011-20I/PTG

• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 52
• Flash Memory Size: 66KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.9
The module has two internal Power modes.
When the ADON bit is ‘1’, the module is in Active mode,
and is fully powered and functional.
When ADON is ‘0’, the module is in Off mode. The dig-
ital and analog portions of the circuit are disabled for
maximum current savings.
In order to return to the Active mode from Off mode, the
user must wait for the ADC circuitry to stabilize.
19.10 ADC Operation During CPU Sleep
19.10.1
When the device enters Sleep mode, all clock sources
to the module are shutdown and stay at logic ‘0’.
If Sleep occurs in the middle of a conversion, the
conversion is aborted. The converter will not continue
with a partially completed conversion on exit from
Sleep mode.
Register contents are not affected by the device
entering or leaving Sleep mode.
The ADC module can operate during Sleep mode if the
ADC clock source is set to RC (ADRC = 1). When the
RC clock source is selected, the ADC module waits one
instruction cycle before starting the conversion. This
allows the SLEEP instruction to be executed, which
eliminates all digital switching noise from the
conversion. When the conversion is complete, the
DONE bit is cleared and the result is loaded into the
ADCBUF register.
If the ADC interrupt is enabled, the device wakes up
from Sleep. If the ADC interrupt is not enabled, the
ADC module is turned off, although the ADON bit
remains set.
© 2008 Microchip Technology Inc.
Module Power-down Modes
and Idle Modes
ADC OPERATION DURING CPU
SLEEP MODE
19.10.2
The ADSIDL bit selects if the module stops on Idle or
continues on Idle. If ADSIDL = 0, the module continues
operation on assertion of Idle mode. If ADSIDL = 1, the
module stops on Idle.
19.11 Effects of a Reset
A device Reset forces all registers to their Reset state.
This forces the ADC module to be turned off, and any
conversion and sampling sequence to be aborted. The
values that are in the ADCBUF registers are not
modified. The ADC Result register contains unknown
data after a Power-on Reset.
19.12 Output Formats
The ADC result is 12 bits wide. The data buffer RAM is
also 12 bits wide. The 12-bit data can be read in one of
four different formats. The FORM<1:0> bits select the
format. Each of the output formats translates to a 16-bit
result on the data bus.
dsPIC30F5011/5013
A/D OPERATION DURING CPU IDLE
MODE
DS70116H-page 135