SC16C2552BIA44 NXP Semiconductors, SC16C2552BIA44 Datasheet - Page 13

• Manufacturer Part Number: SC16C2552BIA44
• Description: UART, 2 CH, 16BYTE FIFO, 16C2552
• Manufacturer: NXP Semiconductors

Specifications of SC16C2552BIA44

• No. Of Channels: 2
• Data Rate: 5Mbps
• Supply Voltage Range: 2.25V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: PLCC
• No. Of Pins: 44
• Svhc: No SVHC (18-Jun-2010)
• Operating: RoHS Compliant
• Uart Features: Independent Transmit & Receive UART Control, Multi-Function Output, Modem Control Functions
• Rohs Compliant: Yes

NXP Semiconductors
SC16C2552B_3
Product data sheet
7.2.1 IER versus Transmit/Receive FIFO interrupt mode operation
7.2.2 IER versus Receive/Transmit FIFO polled mode operation
When the receive FIFO (FCR[0] = logic 1) and receive interrupts (IER[0] = logic 1) are
enabled, the receive interrupts and register status will reflect the following:
When FCR[0] = logic 1, resetting IER[3:0] enables the SC16C2552B in the FIFO polled
mode of operation. In this mode, interrupts are not generated and the user must poll the
LSR register for TX and/or RX data status. Since the receiver and transmitter have
separate bits in the LSR either or both can be used in the polled mode by selecting
respective transmit or receive control bit(s).
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The receive RXRDY interrupt (Level 2 ISR interrupt) is issued to the external CPU
when the receive FIFO has reached the programmed trigger level. It will be cleared
when the receive FIFO drops below the programmed trigger level.
Receive FIFO status will also be reflected in the user accessible ISR register when
the receive FIFO trigger level is reached. Both the ISR register receive status bit and
the interrupt will be cleared when the FIFO drops below the trigger level.
The receive data ready bit (LSR[0]) is set as soon as a character is transferred from
the shift register (RSR) to the receive FIFO. It is reset when the FIFO is empty.
When the Transmit FIFO and interrupts are enabled, an interrupt is generated when
the transmit FIFO is empty due to the unloading of the data by the TSR and UART for
transmission via the transmission media. The interrupt is cleared either by reading the
ISR register or by loading the THR with new data characters.
LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.
LSR[4:1] will provide the type of receive errors or a receive break, if encountered.
LSR[5] will indicate when the transmit FIFO is empty.
LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty.
LSR[7] will show if any FIFO data errors occurred.
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Rev. 03 — 12 February 2009
SC16C2552B
© NXP B.V. 2009. All rights reserved.
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