PCA9555PW NXP Semiconductors, PCA9555PW Datasheet - Page 8

• Manufacturer Part Number: PCA9555PW
• Description: IC, I2C-BUS AND SMBUS I/O PORT, TSSOP24
• Manufacturer: NXP Semiconductors

Specifications of PCA9555PW

• Chip Configuration: 16 Bit
• Bus Frequency: 400kHz
• Ic Interface Type: I2C
• No. Of I/o's: 16
• Supply Voltage Range: 2.3V To 5.5V
• Digital Ic Case Style: TSSOP
• No. Of Pins: 24
• Termination Type: SMD
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
PCA9555_8
Product data sheet
6.2.5 Registers 6 and 7: Configuration registers
6.3 Power-on reset
6.4 I/O port
This register configures the directions of the I/O pins. If a bit in this register is set (written
with ‘1’), the corresponding port pin is enabled as an input with high-impedance output
driver. If a bit in this register is cleared (written with ‘0’), the corresponding port pin is
enabled as an output. Note that there is a high value resistor tied to V
reset, the device's ports are inputs with a pull-up to V
Table 11.
Table 12.
When power is applied to V
condition until V
PCA9555 registers and SMBus state machine will initialize to their default states. The
power-on reset typically completes the reset and enables the part by the time the power
supply is above V
supply, it is necessary to lower it below 0.2 V.
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a
high-impedance input with a weak pull-up to V
V
If the I/O is configured as an output, then either Q1 or Q2 is on, depending on the state of
the Output Port register. Care should be exercised if an external voltage is applied to an
I/O configured as an output because of the low-impedance path that exists between the
pin and either V
Bit
Symbol
Default
Bit
Symbol
Default
DD
to a maximum of 5.5 V.
Configuration port 0 register
Configuration port 1 register
C0.7
C1.7
7
1
7
1
DD
DD
POR
has reached V
or V
. However, when it is required to reset the part by lowering the power
Rev. 08 — 22 October 2009
C0.6
C1.6
SS
6
1
6
1
.
DD
, an internal power-on reset holds the PCA9555 in a reset
C0.5
C1.5
POR
5
1
5
1
. At that point, the reset condition is released and the
16-bit I
C0.4
C1.4
4
1
4
1
2
DD
C-bus and SMBus I/O port with interrupt
. The input voltage may be raised above
C0.3
C1.3
DD
3
1
3
1
.
C0.2
C1.2
2
2
1
1
DD
PCA9555
© NXP B.V. 2009. All rights reserved.
C0.1
C1.1
at each pin. At
1
1
1
1
C0.0
C1.0
0
1
0
1
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