MCP23S08-E/ML Microchip Technology, MCP23S08-E/ML Datasheet - Page 5

• Manufacturer Part Number: MCP23S08-E/ML
• Description: IC, I/O EXPANDER, 8BIT, 10MHZ, QFN-20
• Manufacturer: Microchip Technology

Specifications of MCP23S08-E/ML

• Chip Configuration: 8 Bit
• Bus Frequency: 10MHz
• Ic Interface Type: SPI
• No. Of I/o's: 8
• Supply Voltage Range: 1.8V To 5.5V
• Digital Ic Case Style: QFN
• No. Of Pins: 20
• Interface: SPI
• Number Of I /o: 8
• Interrupt Output: Yes
• Frequency - Clock: 10MHz
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• Includes: POR
• Interface Type: SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: GPIODM-KPLCD - BOARD DEMO LCD GPIO EXP KEYPAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

1.0
The MCP23X08 device provides 8-bit, general
purpose, parallel I/O expansion for I
applications. The two devices differ in the number of
hardware address pins and the serial interface:
• MCP23008 – I
• MCP23S08 – SPI interface; two address pins
The MCP23X08 consists of multiple 8-bit configuration
registers for input, output and polarity selection. The
system master can enable the I/Os as either inputs or
outputs by writing the I/O configuration bits. The data
for each input or output is kept in the corresponding
Input or Output register. The polarity of the Input Port
register can be inverted with the Polarity Inversion
register. All registers can be read by the system master.
1.1
TABLE 1-1:
© 2007 Microchip Technology Inc.
SCL/SCK
SDA/SI
A2/SO
A1
A0
RESET
NC/CS
INT
V
GP0
GP1
GP2
GP3
GP4
GP5
GP6
GP7
V
N/C
SS
DD
Name
Pin
DEVICE OVERVIEW
Pin Descriptions
PDIP/
SOIC
10
11
12
13
14
15
16
17
18
—
1
2
3
4
5
6
7
8
9
2
C interface; three address pins
PINOUT DESCRIPTION
QFN
6, 8
19
20
17
10
11
12
13
14
15
16
18
1
2
3
4
5
7
9
SSOP
10, 11
12
13
14
15
16
17
18
19
20
1
3
2
4
5
6
7
8
9
2
C bus or SPI
Type
Pin
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
O
P
P
I
I
I
I
I
Hardware address input (MCP23008)/
Serial clock input.
Serial data I/O (MCP23008)/Serial data input (MCP23S08).
Serial data output (MCP23S08).
A2 must be biased externally.
Hardware address input. Must be biased externally.
Hardware address input. Must be biased externally.
External reset input. Must be biased externally.
No connect (MCP23008)/External chip select input (MCP23S08).
Interrupt output. Can be configured for active-high, active-low or
open-drain.
Ground.
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or
internal weak pull-up resistor.
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or
internal weak pull-up resistor.
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or
internal weak pull-up resistor.
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or
internal weak pull-up resistor.
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or
internal weak pull-up resistor.
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or
internal weak pull-up resistor.
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or
internal weak pull-up resistor.
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or
internal weak pull-up resistor.
Power.
—
MCP23008/MCP23S08
The interrupt output can be configured to activate
under two conditions (mutually exclusive):
1.
2.
The Interrupt Capture register captures port values at
the time of the interrupt, thereby saving the condition
that caused the interrupt.
The Power-on Reset (POR) sets the registers to their
default values and initializes the device state machine.
The hardware address pins are used to determine the
device address.
When
corresponding input port register state, this is
used to indicate to the system master that an
input state has changed.
When an input state differs from a preconfigured
register value (DEFVAL register).
any
Function
input
state
differs
DS21919E-page 5
from
its