LM97593VH National Semiconductor, LM97593VH Datasheet - Page 46

• Manufacturer Part Number: LM97593VH
• Description: 12BIT ADC, 2CH, DDC/AGC, 128PQFP
• Manufacturer: National Semiconductor

Specifications of LM97593VH

• Resolution (bits): 12bit
• Input Channel Type: Differential
• Data Interface: Serial
• Supply Voltage Range - Analogue: 3V To 3.6V
• Supply Voltage Range - Digital: 1.6V To 2V, 3V To 3.6V
• Supply: RoHS Compliant
• Sampling Rate: 65MSPS
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Not Compliant

www.national.com
11.0 POWER SUPPLY CONSIDERATIONS
The power supply pins should be bypassed with a 10 µF ca-
pacitor and with a 0.1 µF ceramic chip capacitor near each
power pin. Leadless chip capacitors are preferred because
they have low series inductance.
The LM97593 is sensitive to power supply noise. Accordingly,
the noise on the analog supply pins should be kept below 100
mV
No pin should ever have a voltage on it that is in excess of the
supply voltages, not even on a transient basis. Be especially
careful of this during power turn on and turn off.
The V
be operated from a supply equivalent to V
12.0 LAYOUT AND GROUNDING
A proper grounding and proper routing of all signals are es-
sential to ensure accurate conversion. Maintaining separate
analog and digital areas of the board, with the LM97593 be-
tween these areas, is required to achieve specified perfor-
mance.
The ground return for the data outputs (DRGND) carries the
ground current for the output drivers. The output current can
exhibit high transients that could add noise to the conversion
process. To prevent this from happening, the DRGND pins
should NOT be connected to system ground in close proximity
to any of the LM97593's other ground pins.
Capacitive coupling between the typically noisy digital circuit-
ry and the sensitive analog circuitry can lead to poor perfor-
mance. The solution is to keep the analog circuitry separated
from the digital circuitry, and to keep the clock line as short as
possible.
Digital circuits create substantial supply and ground current
transients. The logic noise thus generated could have signif-
icant impact upon system noise performance. The best logic
family to use in systems with A/D converters is one which
employs non-saturating transistor designs, or has low noise
characteristics, such as the 74LS, 74HC(T) and 74AC(T)Q
families. The worst noise generators are logic families that
create the largest supply current transients during clock or
signal edges, like the 74F and the 74AC(T) families.
The effects of the noise generated from the LM97593 output
switching can be minimized through the use of 100Ω resistors
in series with each data output line. Locate these resistors as
close to the LM97593 output pins as possible.
Since digital switching transients are composed largely of
high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise.
This is because of the skin effect. Total surface area is more
important than is total ground plane volume.
Generally, analog and digital lines should cross each other at
90° to avoid crosstalk. To maximize accuracy in high speed,
high resolution systems, however, avoid crossing analog and
digital lines altogether. It is important to keep clock lines as
short as possible and isolated from ALL other lines, including
other digital lines. Even the generally accepted 90° crossing
should be avoided with the clock line as even a little coupling
can cause problems at high frequencies. This is because oth-
er lines can introduce jitter into the clock line, which can lead
to degradation of SNR. Also, the high speed clock can intro-
duce noise into the analog chain.
P-P
DR
.
pin provides power for the output drivers and should
D
.
46
Best performance at high frequencies and at high resolution
is obtained with a straight signal path. That is, the signal path
through all components should form a straight line wherever
possible.
Be especially careful with the layout of inductors. Mutual in-
ductance can change the characteristics of the circuit in which
they are used. Inductors should not be placed side by side,
even with just a small part of their bodies beside each other.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any ex-
ternal component (e.g., a filter capacitor) connected between
the converter's input pins and ground or to the reference input
pin and ground should be connected to a very clean point in
the ground plane.
All analog circuitry (input amplifiers, filters, reference compo-
nents, etc.) should be placed in the analog area of the board.
All digital circuitry and I/O lines should be placed in the digital
area of the board. The LM97593 should be between these
two areas. Furthermore, all components in the reference cir-
cuitry and the input signal chain that are connected to ground
should be connected together with short traces and enter the
ground plane at a single, quiet point. All ground connections
should have a low inductance path to ground.
13.0 DYNAMIC PERFORMANCE
To achieve the best dynamic performance, the clock source
driving the CLK input must be free of jitter. Isolate the ADC
clock from any digital circuitry with buffers, as with the clock
tree shown in Figure 46. The gates used in the clock tree must
be capable of operating at frequencies much higher than
those used if added jitter is to be prevented.
Best performance will be obtained with a differential input
drive, compared with a single-ended drive, as discussed in
Sections 1.3.1 and 1.3.2.
It is good practice to keep the clock line as short as possible
and to keep it well away from any other signals. Other signals
can introduce jitter into the clock signal, which can lead to
reduced SNR performance, and the clock can introduce noise
into other lines. Even lines with 90° crossings have capacitive
coupling, so try to avoid even these 90° crossings of the clock
line.
FIGURE 46. Isolating the ADC Clock from other Circuitry
with a Clock Tree
30008756