LM97593VH National Semiconductor, LM97593VH Datasheet - Page 34

• Manufacturer Part Number: LM97593VH
• Description: 12BIT ADC, 2CH, DDC/AGC, 128PQFP
• Manufacturer: National Semiconductor

Specifications of LM97593VH

• Resolution (bits): 12bit
• Input Channel Type: Differential
• Data Interface: Serial
• Supply Voltage Range - Analogue: 3V To 3.6V
• Supply Voltage Range - Digital: 1.6V To 2V, 3V To 3.6V
• Supply: RoHS Compliant
• Sampling Rate: 65MSPS
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Not Compliant

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on the rising edge of SCK (or falling edge if the SCK_POL bit
in the input control register is set high). Data should be cap-
tured on the falling edge of SCK (rising if SCK_POL=1). The
chip sends the I data first by setting SFS high (or low if
SFS_POL in the input control register is set high) for one clock
cycle, and then transmitting the data, MSB first, on as many
SCK cycles as are necessary. Without a pause, the Q data is
transferred next as shown in Figure 34(a). If the PACKED
control bit is high, then the I and Q components are sent as a
double length word with only one SFS strobe as shown in
Figure 34(b). If both channels are multiplexed out the same
serial pin, then the subsequent I/Q channel words will be
transmitted immediately following the first I/Q pair as shown
in Figure 34(c). Figure 34(c) also shows how SFS_MODE=1
allows the SFS signal to be used to identify the A and B chan-
nels in the TDM serial transmission. The serial output rate is
programmed by the RATE register to CK divided by 1, 2, 4,
8, 16, or 32. The serial interface will not work properly if the
programmed rate of SCK is insufficient to clock out all the bits
in one OSP.
5.2 Serial Port Daisy-Chain Mode
Two LM97593s can be connected in series so that a single
DSP serial port can receive four DDC output channels. This
mode is enabled by setting the SDC_EN bit to ‘1’ on the serial
daisy-chan (SDC) master. The SDC master is the LM97593
which is connected to the DSP while the SDC slave’s serial
output drives the master. The SDC master’s RATE register
must be set so that its SCK rate is twice that of the SDC slave,
the SDC master must have MUX_MODE=1, the SDC slave
must have MUX_MODE=0 and PACKED=1, and both chips
must come out of a MR or SI event within four CK periods of
each other. In this configuration, the master’s serial output
data is shifted out to the DSP and then the slave’s serial data
is shifted out. All the serial output data will be muxed onto the
master’s AOUT pin as shown in Figure 35.
5.3 Serial Port Output Number Formats
Several numeric formats are selectable using the FORMAT
control register. The I/Q samples can be rounded to 16 or 24
bits, or truncated to 8 bits. The packed mode works as de-
scribed above for these fixed point formats. A floating point
format with 138dB of dynamic range in 12 bits is also provid-
ed. The mantissa (m) is 8 bits and the exponent (e) is 4 bits.
The MSB of each segment is transmitted first. When the
packed mode is selected, the I/Q samples are packed re-
FIGURE 35. Serial Daisy-Chain Mode
34
gardless of the state of MUX_MODE, and the data is sent as
mI/eI/eQ/ mQ which allows the two exponents to form an 8-
bit word. This is shown in Figure 34(d). For all formats, once
the defined length of the word is complete, SCK stops tog-
gling.
5.4 Parallel Outputs
Output data from the channels can also be taken from a 16-
bit parallel port. A 3-bit word applied to the POUT_SEL[2:0]
pins determines which 16-bit segment is multiplexed to the
parallel port. Table 3 defines this mapping. To allow for buss-
ing of multiple chips, the parallel port is tri-stated unless
POUT_EN is low. The RDY signal indicates the start of an
OSP and that new data is ready at the parallel output. The
user has one OSP to cycle through whichever registers are
needed. The RATE register must be set so that each OSP is
at least 5 SCK periods.
5.4.1 Parallel Port Output Numeric Formats
The I/Q samples can be rounded to 16 or 24 bits or the full 32
bit word can be read. By setting the word size to 32 bits it is
possible to read out the top 16-bits and only observe the top
8 bits if desired. Additionally, the output samples can be for-
matted as floating point numbers with an 8-bit mantissa and
a 4 bit exponent. For the fixed-point formats, the valid bits are
justified into the MSBs of the registers of Table 3 and
all other bits are set to zero. For the floating point format, the
valid bits are placed in the upper 16-bits of the appropriate
channel register using the format 0000/eI/mI for the I samples.
TABLE 3. Register Selection for Parallel Output
POUT_SEL
0
1
2
3
4
5
6
7
Normal Register
QA upper 16-bits
QB upper 16-bits
QA lower 16-bits
QB lower 16-bits
IA upper 16-bits
IB upper 16-bits
IA lower 16-bits
B lower 16-bits
Contents
30008733
0000/eQA/mQA
0000/eQB/mQB
Floating Point
0000/eIA/mIA
0000/eIB/mIB
Contents
Register
0x0000
0x0000
0x0000
0x0000