ADC108S052CIMT National Semiconductor, ADC108S052CIMT Datasheet - Page 5

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ADC108S052CIMT

Manufacturer Part Number
ADC108S052CIMT
Description
10BIT ADC, 8CH, POWERWISE, TSSOP16
Manufacturer
National Semiconductor
Datasheet

Specifications of ADC108S052CIMT

Resolution (bits)
10bit
Input Channel Type
Single Ended
Data Interface
Serial, SPI
Supply Voltage Range - Analogue
2.7V To 5.25V
Supply Voltage Range - Digital
2.7V To 5.25V
Supply
RoHS Compliant
Sampling Rate
500kSPS
Rohs Compliant
Yes

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Symbol
ADC108S052 Timing Specifications
The following specifications apply for V
200 kSPS to 500 kSPS, and C
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, V
The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two.
Note 4: The absolute maximum junction temperature (T
junction-to-ambient thermal resistance (θ
TSSOP, θ
of this device under normal operation is a maximum of 12 mW. The values for maximum power dissipation listed above will be reached only when the ADC108S052
is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed).
Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO ohms
Note 6: Reflow temperature profiles are different for lead-free packages.
Note 7: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 8: Data sheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Note 9: Clock may be in any state (high or low) when CS goes high. Setup and hold restrictions apply only to CS going high.
t
t
t
t
DACC
DHLD
t
CSH
CSS
t
t
t
t
t
DIS
EN
DS
DH
CH
CL
JA
CS Hold Time after SCLK Rising
Edge
CS Setup Time prior to SCLK Rising
Edge
CS Falling Edge to DOUT enabled
DOUT Access Time after SCLK
Falling Edge
DOUT Hold Time after SCLK Falling
Edge
DIN Setup Time prior to SCLK
Rising Edge
DIN Hold Time after SCLK Rising
Edge
SCLK High Time
SCLK Low Time
CS Rising Edge to DOUT
High-Impedance
is 96˚C/W, so P
D
Parameter
MAX = 1,200 mW at 25˚C and 625 mW at the maximum operating ambient temperature of 105˚C. Note that the power consumption
L
JA
= 50pF. Boldface limits apply for T
), and the ambient temperature (T
A
= V
D
J
max) for this device is 150˚C. The maximum allowable power dissipation is dictated by T
= +2.7V to +5.25V, AGND = DGND = 0V, f
(Note 9)
(Note 9)
DOUT falling
DOUT rising
A
), and can be calculated using the formula P
Conditions
5
IN
<
AGND or V
A
= T
MIN
IN
>
to T
V
A
or V
MAX
D
), the current at that pin should be limited to 10 mA.
: all other limits T
Typical
SCLK
2.4
0.9
17
0
5
5
4
3
3
= 3.2 MHz to 8 MHz, f
D
MAX = (T
(Note 7)
Limits
t
t
0.4 x
0.4 x
J
SCLK
SCLK
A
max − T
10
10
30
27
10
10
20
20
= 25˚C.
A
)/θ
JA
www.national.com
. In the 16-pin
ns (max)
ns (max)
ns (max)
ns (max)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (typ)
SAMPLE
Units
J
max, the
=

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