ADC108S052CIMT National Semiconductor, ADC108S052CIMT Datasheet - Page 15

• Manufacturer Part Number: ADC108S052CIMT
• Description: 10BIT ADC, 8CH, POWERWISE, TSSOP16
• Manufacturer: National Semiconductor

Specifications of ADC108S052CIMT

• Resolution (bits): 10bit
• Input Channel Type: Single Ended
• Data Interface: Serial, SPI
• Supply Voltage Range - Analogue: 2.7V To 5.25V
• Supply Voltage Range - Digital: 2.7V To 5.25V
• Supply: RoHS Compliant
• Sampling Rate: 500kSPS
• Rohs Compliant: Yes

2.0 Applications Information
2.1 TYPICAL APPLICATION CIRCUIT
A typical application is shown in Figure 8. The split analog
and digital supply pins are both powered in this example by
the National LP2950 low-dropout voltage regulator. The ana-
log supply is bypassed with a capacitor network located
close to the ADC108S052. The digital supply is separated
from the analog supply by an isolation resistor and bypassed
with additional capacitors. The ADC108S052 uses the ana-
log supply (V
2.2 POWER SUPPLY CONSIDERATIONS
There are three major power supply concerns with this prod-
uct: power supply sequencing, power management, and the
effect of digital supply noise on the analog supply.
2.2.1 Power Supply Sequence
The ADC108S052 is a dual-supply device. The two supply
pins share ESD resources, so care must be exercised to
ensure that the power is applied in the correct sequence. To
avoid turning on the ESD diodes, the digital supply (V
cannot exceed the analog supply (V
not even on a transient basis. Therefore, V
before or concurrently with V
2.2.2 Power Management
The ADC108S052 is fully powered-up whenever CS is low
and fully powered-down whenever CS is high, with one
exception. If operating in continuous conversion mode, the
ADC108S052 automatically enters power-down mode be-
tween SCLK’s 16th falling edge of a conversion and SCLK’s
1st falling edge of the subsequent conversion (see Figure 1).
In continuous conversion mode, the ADC108S052 can per-
form multiple conversions back to back. Each conversion
requires 16 SCLK cycles and the ADC108S052 will perform
conversions continuously as long as CS is held low. Con-
tinuous mode offers maximum throughput.
In burst mode, the user may trade off throughput for power
consumption by performing fewer conversions per unit time.
This means spending more time in power-down mode and
less time in normal mode. By utilizing this technique, the
user can achieve very low sample rates while still utilizing an
SCLK frequency within the electrical specifications. The
Power Consumption vs. SCLK curve in the Typical Perfor-
A
) as its reference voltage, so it is very impor-
D
.
A
) by more than 300 mV,
FIGURE 8. Typical Application Circuit
A
must ramp up
D
)
15
tant that V
power requirements of the ADC108S052, it is also possible
to use a precision reference as a power supply.
To minimize the error caused by the changing input capaci-
tance of the ADC108S052, a capacitor is connected from
each input pin to ground. The capacitor, which is much larger
than the input capacitance of the ADC108S052 when in track
mode, provides the current to quickly charge the sampling
capacitor of the ADC108S052. An isolation resistor is added
to isolate the load capacitance from the input source.
mance Curves section shows the typical power consumption
of the ADC108S052. To calculate the power consumption
(P
mode (t
add the fraction of time spent in shutdown mode (t
plied by the shutdown mode power consumption (P
shown in Figure 9.
2.2.3 Power Supply Noise Considerations
The charging of any output load capacitance requires cur-
rent from the digital supply, V
from the supply to charge the output capacitance will cause
voltage variations on the digital supply. If these variations are
large enough, they could degrade SNR and SINAD perfor-
mance of the ADC. Furthermore, if the analog and digital
supplies are tied directly together, the noise on the digital
supply will be coupled directly into the analog supply, caus-
ing greater performance degradation than would noise on
the digital supply alone. Similarly, discharging the output
capacitance when the digital output goes from a logic high to
a logic low will dump current into the die substrate, which is
resistive. Load discharge currents will cause "ground
bounce" noise in the substrate that will degrade noise per-
formance if that current is large enough. The larger the
C
), simply multiply the fraction of time spent in the normal
N
FIGURE 9. Power Consumption Equation
) by the normal mode power consumption (P
A
be kept as clean as possible. Due to the low
D
. The current pulses required
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S
) multi-
N
), and
S
) as