ADC108S052CIMT National Semiconductor, ADC108S052CIMT Datasheet - Page 14

• Manufacturer Part Number: ADC108S052CIMT
• Description: 10BIT ADC, 8CH, POWERWISE, TSSOP16
• Manufacturer: National Semiconductor

Specifications of ADC108S052CIMT

• Resolution (bits): 10bit
• Input Channel Type: Single Ended
• Data Interface: Serial, SPI
• Supply Voltage Range - Analogue: 2.7V To 5.25V
• Supply Voltage Range - Digital: 2.7V To 5.25V
• Supply: RoHS Compliant
• Sampling Rate: 500kSPS
• Rohs Compliant: Yes

www.national.com
1.0 Functional Description
neously and the ADC enters track mode. While there is no
timing restriction with respect to the falling edges of CS and
SCLK, see Figure 3 for setup and hold time requirements for
the falling edge of CS with respect to the rising edge of
SCLK.
During each conversion, data is clocked into a control reg-
ister through the DIN pin on the first 8 rising edges of SCLK
1.3 ADC108S052 TRANSFER FUNCTION
The output format of the ADC108S052 is straight binary.
Code transitions occur midway between successive integer
LSB values. The LSB width for the ADC108S052 is V
1024. The ideal transfer characteristic is shown in Figure 6.
The transition from an output code of 00 0000 0000 to a
code of 00 0000 0001 is at 1/2 LSB, or a voltage of V
2048. Other code transitions occur at steps of one LSB.
Bit 7 (MSB)
ADD2
DONTC
0
0
0
0
1
1
1
1
Bit #:
7, 6, 2, 1, 0
5
4
3
FIGURE 6. Ideal Transfer Characteristic
TABLE 3. Input Channel Selection
ADD1
0
0
1
1
0
0
1
1
DONTC
Symbol:
DONTC
ADD2
ADD1
ADD0
Bit 6
ADD0
0
1
0
1
0
1
0
1
ADD2
TABLE 2. Control Register Bit Descriptions
Input Channel
Bit 5
Description
Don’t care. The values of these bits do not affect the device.
These three bits determine which input channel will be sampled and
converted at the next conversion cycle. The mapping between codes and
channels is shown in Table 3.
IN0 (Default)
IN1
IN2
IN3
IN4
IN5
IN6
IN7
TABLE 1. Control Register Bits
(Continued)
20164411
ADD1
Bit 4
A
A
/
/
14
after the fall of CS. The control register is loaded with data
indicating the input channel to be converted on the subse-
quent conversion (see Tables 1, 2, 3).
The user does not need to incorporate a power-up delay or
dummy conversions as the ADC108S052 is able to acquire
the input signal to full resolution in the first conversion im-
mediately following power-up. The first conversion result
after power-up will be that of IN0.
1.4 ANALOG INPUTS
An equivalent circuit for one of the ADC108S052’s input
channels is shown in Figure 7. Diodes D1 and D2 provide
ESD protection for the analog inputs. The operating range
for the analog inputs is 0 V to V
will cause the ESD diodes to conduct and result in erratic
operation.
The capacitor C1 in Figure 7 has a typical value of 3 pF and
is mainly the package pin capacitance. Resistor R1 is the on
resistance of the multiplexer and track / hold switch and is
typically 500 ohms. Capacitor C2 is the ADC108S052 sam-
pling capacitor, and is typically 30 pF. The ADC108S052 will
deliver best performance when driven by a low-impedance
source (less than 100 ohms). This is especially important
when using the ADC108S052 to sample dynamic signals.
Also important when sampling dynamic signals is a band-
pass or low-pass filter which reduces harmonics and noise in
the input. These filters are often referred to as anti-aliasing
filters.
1.5 DIGITAL INPUTS AND OUTPUTS
The ADC108S052’s digital inputs (SCLK, CS, and DIN) have
an operating range of 0 V to V
latch-up and may be asserted before the digital supply (V
without any risk. The digital output (DOUT) operating range
is controlled by V
(min) while the output low voltage is 0.4V (max).
ADD0
Bit 3
FIGURE 7. Equivalent Input Circuit
DONTC
Bit 2
D
. The output high voltage is V
DONTC
A
Bit 1
. Going beyond this range
A
. They are not prone to
20164414
DONTC
Bit 0
D
- 0.5V
D
)