LIS3LV02DLTR STMicroelectronics, LIS3LV02DLTR Datasheet - Page 16

• Manufacturer Part Number: LIS3LV02DLTR
• Description: IC MEMS INERTL SENSOR 3AX LGA16
• Manufacturer: STMicroelectronics

Specifications of LIS3LV02DLTR

• Featured Product: STM32 Cortex-M3 Companion Products
• Axis: X, Y, Z
• Acceleration Range: ±2g, 6g
• Sensitivity: 1024LSB/g, 340LSB/g
• Voltage - Supply: 2.16 V ~ 3.6 V
• Output Type: Digital
• Bandwidth: 40Hz ~ 2.56kHz Selectable
• Interface: I²C, SPI
• Mounting Type: Surface Mount
• Package / Case: 16-LGA
• Family Name: LIS3LV02DL
• Package Type: LGA
• Operating Supply Voltage (min): 2.16V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 4.4mm
• Product Length (mm): 7.5mm
• Mounting: Surface Mount
• Pin Count: 16
• Sensing Axis: X, Y, Z
• Acceleration: 2 g, 6 g
• Digital Output - Number Of Bits: 12 bit, 16 bit
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.16 V
• Supply Current: 0.65 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Digital Output - Bus Interface: I2C, SPI
• For Use With: 497-8261 - BOARD EVAL BASED ON LIS3LV02DL497-5069 - EVAL BOARD 3AXIS MEMS ACCELLRMTR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8415-2; LIS3LV02DLTR

Mechanical and electrical specifications
2.3.2
Table 7.
1. Data based on standard I
2. A device must internally provide an hold time of at least 300ns for the SDA signal (referred to VIHmin of the SCL signal) to
3. Cb = total capacitance of one bus line, in pF
16/48
t
t
r(SDA)
f(SDA)
bridge the undefined region of the falling edge of SCL
t
Symbol
t
t
t
w(SP:SR)
w(SCLH)
t
w(SCLL)
t
su(SDA)
t
f
h(SDA)
t
su(SR)
su(SP)
(SCL)
h(ST)
t
t
r(SCL)
f(SCL)
I
Subject to general operating conditions for Vdd and Top.
I2C slave timing values
Figure 4.
4.Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both port
2
C - Inter IC control interface
SCL clock frequency
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
Repeated START condition
setup time
STOP condition setup time
Bus free time between STOP
and START condition
SCL
SDA
t
f(SDA)
2
Parameter
C protocol requirement, not tested in production
I
2
t
C slave timing diagram
h(ST)
START
t
w(SCLL)
t
r(SDA)
t
w(SCLH)
I
2
t
C standard mode
su(SDA)
Min
250
0
4.7
4.0
4.7
4.7
0
4
4
(2)
t
r(SCL)
(4)
t
f(SCL)
t
h(SDA)
1000
Max
3.45
100
300
(1)
20 + 0.1C
20 + 0.1C
Min
100
0
1.3
0.6
0.6
0.6
0.6
1.3
I
0
(2)
2
C fast mode
b
b
(3)
(3)
t
su(SR)
t
su(SP)
t
w(SP:SR)
Max
400
300
300
(1)
0.9
LIS3LV02DL
REPEATED
START
STOP
START
Unit
KHz
µs
ns
µs
ns
µs