LIS35DETR STMicroelectronics, LIS35DETR Datasheet

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... The sensing element, capable of detecting the acceleration, is manufactured using a dedicated Table 1. Device summary Order code LIS35DE LIS35DETR April 2009 process developed produce inertial sensors and actuators in silicon. The IC interface is manufactured using a CMOS process that allows to design a dedicated circuit which is trimmed to better match the sensing element characteristics ...

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Contents Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 Block ...

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LIS35DE 7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of tables List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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LIS35DE Table 50. CLICK_SRC (39h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of figures List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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LIS35DE 1 Block diagram and pin description 1.1 Block diagram Figure 1. Block diagram REFERENCE 1.2 Pin description Figure 2. Pin connection Y 6 CHARGE AMPLIFIER A/D MUX CONVERTER TRIMMING CLOCK CIRCUITS Z ...

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Block diagram and pin description Table 2. Pin description Pin 8/39 Name Vdd_IO Power supply for I/O pins GND 0V supply Reserved Connect to Vdd GND ...

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LIS35DE 2 Mechanical and electrical specifications 2.1 Mechanical characteristics T = 25°C unless otherwise noted Table 3. Mechanical characteristics @ Vdd=2.5 V Symbol Parameter FS Measurement range Dres Device resolution So Sensitivity Sensitivity change vs TCSO temperature Typical zero-g level ...

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Mechanical and electrical specifications 2.2 Electrical characteristics T = 25°C unless otherwise noted Table 4. Electrical characteristics @ Vdd=2.5 V Symbol Parameter Vdd Supply voltage Vdd_IO I/O pins supply voltage Idd Supply current Current consumption in IddPdn power-down mode Digital ...

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LIS35DE 2.3 Communication interface characteristics 2.3.1 SPI - serial peripheral interface Subject to general operating conditions for Vdd and Top. Table 5. SPI slave timing values Symbol tc(SPC) SPI clock cycle fc(SPC) SPI clock frequency tsu(CS) CS setup time th(CS) ...

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Mechanical and electrical specifications 2 2.3 Inter IC control interface Subject to general operating conditions for Vdd and top. 2 Table slave timing values Symbol Parameter f SCL clock frequency (SCL) t SCL clock ...

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LIS35DE 2.4 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to ...

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Mechanical and electrical specifications 2.5 Terminology 2.5.1 Sensitivity Sensitivity describes the gain of the sensor and can be determined e.g. by applying 1g acceleration to it. As the sensor can measure DC accelerations this can be done easily by pointing ...

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LIS35DE 3 Functionality The LIS35DE is a ultracompact, low-power, digital output 3-axis linear accelerometer packaged in a LGA package. The complete device includes a sensing element and an IC interface able to take the information from the sensing element and ...

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Application hints 4 Application hints Figure 5. LIS35DE electrical connection Vdd 10uF 100nF GND The device core is supplied through Vdd line while the I/O pads are supplied through Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 µF ...

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LIS35DE 5 Digital interfaces The registers embedded inside the LIS35DE may be accessed through both the I SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. The serial interfaces are mapped ...

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Digital interfaces 2 5.1 operation The transaction on the bus is started through a START (ST) signal. A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held ...

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LIS35DE Table 12. Transfer when Master is writing multiple bytes to slave Master ST Slave Table 13. Transfer when Master is receiving (reading) one byte of data from slave Master ST SAD + W Slave Table 14. Transfer when Master ...

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Digital interfaces Figure 6. Read and write protocol CS SPC SDI SDO CS is the Serial Port Enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at ...

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LIS35DE 5.2.1 SPI read Figure 7. SPI read protocol CS SPC SDI SDO The SPI read command is performed with 16 clock pulses. Multiple byte read command is performed adding blocks of 8 clock pulses at the previous one. bit ...

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Digital interfaces The SPI write command is performed with 16 clock pulses. Multiple byte write command is performed adding blocks of 8 clock pulses at the previous one. bit 0: WRITE bit. The value is 0. bit 1: MS bit. ...

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LIS35DE 6 Register mapping The table given below provides a listing of the 8 bit registers embedded in the device and the related address: Table 16. Register address map Name Reserved (do not modify) Ctrl_Reg1 Ctrl_Reg2 Ctrl_Reg3 HP_filter_reset Reserved (do ...

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Register mapping Table 16. Register address map (continued) Name CLICK_Latency CLICK_Window Registers marked as Reserved must not be changed. The writing to those registers may cause permanent damages to the device. The content of the registers that are loaded at ...

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LIS35DE 7 Register description The device contains a set of registers which are used to control its behavior and to retrieve acceleration data. The registers address, made of 7 bits, is used to identify them and to write the data ...

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Register description 7.2 CTRL_REG2 (21h) Table 19. CTRL_REG2 (21h) register SIM BOOT Table 20. CTRL_REG2 (21h) register description SIM SPI Serial Interface Mode selection. Default value: 0 (0: 4-wire interface; 1: 3-wire interface) BOOT Reboot memory content. Default value: 0 ...

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LIS35DE Table 21. High pass filter cut-off frequency configuration (continued) HP_coeff2 7.3 CTRL_REG3 [interrupt CTRL register] (22h) Table 22. CTRL_REG3 [interrupt CTRL register] (22h) register IHL PP_OD Table 23. CTRL_REG3 [interrupt CTRL register] (22h) register description IHL Interrupt ...

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Register description 7.5 STATUS_REG (27h) Table 25. STATUS_REG (27h) register ZXYOR ZOR Table 26. STATUS_REG (27h) register description X, Y and Z axis Data Overrun. Default value: 0 ZYXOR (0: no overrun has occurred; 1: new data has over written ...

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LIS35DE Y axis output data. 7.8 OUT_Z (2Dh) Table 29. OUT_Z (2Dh) register ZD7 ZD6 Z axis output data. 7.9 FF_WU_CFG_1 (30h) Table 30. FF_WU_CFG_1 (30h) register AOI LIR Table 31. FF_WU_CFG_1 (30h) register description And/Or combination of Interrupt events. ...

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Register description 7.10 FF_WU_SRC_1 (31h) Table 32. FF_WU_SRC_1 (31h) register X IA Table 33. FF_WU_SRC_1 (31h) register description Interrupt Active. Default value (0: no interrupt has been generated; 1: one ore more interrupt has been generated) Z High. ...

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LIS35DE 7.12 FF_WU_DURATION_1 (33h) Table 36. FF_WU_DURATION_1 (33h) register D7 D6 Table 37. FF_WU_DURATION_1 (33h) register description Duration register for Free-Fall/Wake-Up interrupt 1. Duration step and maximum value depend on the ODR chosen. Step 2.5 msec, from ...

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Register description 7.14 FF_WU_SRC_2 (35h) Table 40. FF_WU_SRC_2 (35h) register X IA Table 41. FF_WU_SRC_2 (35h) register description IA Interrupt Active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupt event has been generated) ZH ...

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LIS35DE 7.16 FF_WU_DURATION_2 (37h) Table 44. FF_WU_DURATION_2 (37h) register D7 D6 Table 45. FF_WU_DURATION_2 (37h) register description Duration value. Default value: 0000 0000 Duration register for Free-Fall/Wake-Up interrupt 2. Duration step and maximum value depend on the ...

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Register description 7.17 CLICK_CFG (38h) Table 46. CLICK_CFG (38h) register - LIR Table 47. CLICK_CFG (38h) register description Latch Interrupt request into CLICK_SRC reg with the CLICK_SRC reg refreshed by reading CLICK_SRC reg. Default value: 0 LIR (0: interrupt request ...

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LIS35DE 7.18 CLICK_SRC (39h) Table 49. CLICK_SRC (39h) register X IA Table 50. CLICK_SRC (39h) register description Interrupt Active. Default value (0: no interrupt has been generated; 1: one or more interrupt event has been generated) Double click ...

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Register description Table 54. CLICK_THSZ (3Ch) register description THSz3 - THSz0 From 0.5g (0001) to 7.5g (1111) with step of 0.5g. 7.21 CLICK_TimeLimit (3Dh) Table 55. CLICK_TimeLimit (3Dh) register Dur7 Dur6 From 0 to 127.5msec with step of 0.5msec. 7.22 ...

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LIS35DE 8 Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK ...

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Revision history 9 Revision history Table 58. Document revision history Date 29-Apr-2009 38/39 Revision 1 Initial release Doc ID 15594 Rev 1 LIS35DE Changes ...

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... LIS35DE Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...