1323XNSK Freescale Semiconductor, 1323XNSK Datasheet - Page 31

• Manufacturer Part Number: 1323XNSK
• Description: KIT DEV FOR 1323X_NETWORK
• Manufacturer: Freescale Semiconductor
• Type: Transceiver, 802.15.4r

Specifications of 1323XNSK

• Frequency: 2.4GHz
• Interface Type: SPI
• For Use With/related Products: MC1323x
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.13 FLASH Specifications
This section provides details about program/erase times and program-erase endurance for the FLASH
memory. Program and erase operations do not require any special power sources other than the normal
V
may only be executed with CPU clock programmed for 32 MHz (default)
Freescale Semiconductor
1
2
signal) to bridge the undefined region of the falling edge of SCL.
3
4
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal.
If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t
+ t
released.
5
SCL clock frequency (when source)
Hold time (repeated) START condition.
After this period, the first clock pulse is generated
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time
Data setup time
Rise time for both SDA and SCL signals
Fall time for both SDA and SCL signals
Bus free time between a STOP and START condition
Capacitive load for each bus line
DD
All values referred to V
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
The maximum t
A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement t
SU;DAT
C
b
= total capacitance of one bus line in pF. If mixed with Hs-mode devices, the faster fall-times are allowed.
supply. The FLASH is 81920 bytes organized as 80 pages by 1024 bytes. FLASH erase and program
= 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is
FLASH erase and program may only be executed with CPU clock
programmed for 32 MHz (default). FLASH operations are hardware state
machine controlled. User code need not count cycles. The following
information is supplied for calculating approximate time to program and
erase.
HD;DAT
IHmin
has only to be met if the device does not stretch the LOW period (t
Parameter
and V
ILmax
Table 18. I
MC1323x Advance Information, Rev. 1.2
levels
2
C Signal AC Specifications
NOTE
t
Symbol
t
SHD;DAT
t
t
HD;STA
SU:DAT
SU;STA
t
t
f
t
HIGH
LOW
SCL
BUF
C
t
t
r
f
b
Standard-Mode
Min
250
4.0
4.7
4.0
4.7
4.7
0
0
-
-
-
2
1
3.45
1000
Max
100
300
400
-
-
-
-
-
-
LOW
3
) of the SCL signal.
0.1C
0.1C
100
20 +
20 +
Min
0.6
1.3
0.6
0.6
1.3
0
Fast-Mode
0
-
IHmin
2
4
b
b
SU;DAT
5
5
of the SCL
Max
0.9
150
300
300
400
>= 250 ns
-
-
-
-
-
-
r max
3
Unit
kHz
pF
μs
μs
μs
μs
μs
ns
ns
ns
μs
31