MPC8572EAMC Freescale Semiconductor, MPC8572EAMC Datasheet - Page 21

• Manufacturer Part Number: MPC8572EAMC
• Description: MPC8572 AMC RAPID SYSTEM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8572EAMC

• Contents: Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MPC8572E

1
Note:
Check the default positions of the board first and ensure that the board is operational before changing any
settings. Please also ensure that the selected settings are within the maximum supported operating
characteristics of the device.
4.2
There is one jumper on the board as described in
System CPLD from the JTAG chain.
Freescale Semiconductor
SW500.4
SW500.5
SW500.6
SW500.7
SW500.8
SW501.1
SW501.2
SW501.3
SW501.4
Feature
Default
Note: If the Reset CPLD is blank, then position 1-2 must be used to program it.
[OFF = 1, ON = 0)
Default Settings
Jumpers
Jumper
J12
OFF
OFF
OFF
OFF
OFF
ON
ON
ON
ON
Selects the Reset and System CPLD JTAG chain.
• Position 1-2: only Reset CPLD is in the chain
• Position 2-3: both Reset and System CPLDs are in the chain.
MPC8572EAMC Advanced Mezzanine Card User Guide, Rev. 1.2
Table 4-1. MPC8572EAMC DIP Switch Listing (continued)
[SW500.4:5] = ON:ON. MPC8572E acts as agent on all interfaces
[SW500.4:5] = OFF:ON. MPC8572E acts as end point on PCIE #1 host
[SW500.4:5] = ON:OFF. MPC8572E acts as end point on SRIO & PCIE #1 host
[SW500.4:5] = OFF:OFF. MPC8572E acts as the host processor
[SW500.6:8] = OFF:ON:ON. IO Port Selection = SRIO 100-MHz clock, 2.5 Gbps (x4)
[SW500.6:8] = ON:OFF:ON. IO Port Selection = SRIO/PCIE 100-MHz clock, 2.5 Gbps
[SW500.6:8] = OFF:OFF:ON. IO Port Selection = SRIO/PCIE 100-MHz clock, 1.25/2.5 Gbps (x4)
[SW500.6:8] = OFF:ON:OFF. IO Port Selection = SRIO 100-MHz clock, 1.25 Gbps (x4)
[SW500.6:8] = ON:ON:OFF. IO Port Selection = SRIO 125 MHz, 3.125 Gbps (x4)
[SW501.1] = ON Boot Sequence Configuration = Boot Sequencer Enabled
[SW501.1] = OFF Boot Sequence Configuration = Boot Sequencer Disabled
CPU Boot Config:
[SW501.2:3] = ON:ON.CPU boot hold-off both cores
[SW501.2:3] = OFF:ON. E500 Core 0 allowed to boot, Core 1 in boot hold-off
[SW501.2:3] = ON:OFF. E500 Core 1 allowed to boot, Core 0 in boot hold-off
[SW501.2:3] = OFF:OFF. Both cores boot without external master
RIO System Size:
[SW501.4] = ON. Large system size, up to 65,536 devices
[SW501.4] = OFF. Small system size, up to 256 devices
Table 4-2. Jumper Position
Table
SW501
Description
4-2. This jumper is used to include or isolate the
Comments
1
1
Controls and Indicators
1
1
1
4-3