MCB1114 Keil, MCB1114 Datasheet - Page 22

• Manufacturer Part Number: MCB1114
• Description: BOARD EVALUATION FOR NXP LPC1114
• Manufacturer: Keil

Specifications of MCB1114

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
LPC1111_12_13_14_0
Objective data sheet
7.10.1 Features
7.11.1 Features
7.12 General purpose external event counters/timers
7.11 10-bit ADC
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
controlled by more than one bus master connected to it.
The LPC1111/12/13/14 contains one ADC. It is a single 10-bit successive approximation
ADC with eight channels.
The LPC1111/12/13/14 includes two 32-bit counter/timers and two 16-bit counter/timers.
The counter/timer is designed to count cycles of the system derived clock. It can optionally
generate interrupts or perform other actions at specified timer values, based on four
match registers. Each counter/timer also includes one capture input to trap the timer value
when an input signal transitions, optionally generating an interrupt.
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The I
also supports Fast mode plus with bit rates up to 1 Mbit/s.
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
The I
10-bit successive approximation ADC.
Input multiplexing among 8 pins.
Power-down mode.
Measurement range 0 V to V
10-bit conversion time ≥ 2.44 μs.
Burst conversion mode for single or multiple inputs.
Optional conversion on transition of input pin or Timer Match signal.
Individual result registers for each ADC channel to reduce interrupt overhead.
2
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2
C-interface is a standard I
C-bus can be used for test and diagnostic purposes.
C-bus controller supports multiple address recognition and a bus monitor mode.
Rev. 00.11 — 13 November 2009
DD(3V3)
2
C compliant bus interface with open-drain pins. I
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2
LPC1111/12/13/14
C is a multi-master bus and can be
© NXP B.V. 2009. All rights reserved.
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