MCB1114 Keil, MCB1114 Datasheet - Page 20

• Manufacturer Part Number: MCB1114
• Description: BOARD EVALUATION FOR NXP LPC1114
• Manufacturer: Keil

Specifications of MCB1114

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
LPC1111_12_13_14_0
Objective data sheet
7.5.2 Interrupt sources
7.7.1 Features
7.6 IOCONFIG block
7.7 Fast general purpose parallel I/O
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags. Individual interrupt flags may also represent more than one interrupt
source.
Any GPIO pin (total of up to 42 pins) regardless of the selected function, can be
programmed to generate an interrupt on a level, or rising edge or falling edge, or both.
The IOCONFIG block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on-chip peripherals.
Peripherals should be connected to the appropriate pins prior to being activated and prior
to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is
not mapped to a related pin should be considered undefined.
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The value of the
output register may be read back as well as the current state of the port pins.
LPC1111/12/13/14 use accelerated GPIO functions:
Additionally, any GPIO pin (total of up to 42 pins) providing a digital function can be
programmed to generate an interrupt on a level, a rising or falling edge, or both.
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In the LPC1111/12/13/14, the NVIC supports 32 vectored interrupts including up to 13
inputs to the start logic from individual GPIO pins.
8 programmable interrupt priority levels, with hardware priority level masking
Relocatable vector table.
Software interrupt generation.
GPIO registers are a dedicated AHB peripheral and are accessed through the AHB so
that the fastest possible I/O timing can be achieved.
Entire port value can be written in one instruction.
Bit level set and clear registers allow a single instruction to set or clear any number of
bits in one port.
Direction control of individual bits.
All I/O default to inputs with pull-ups enabled after reset.
Pull-up/pull-down resistor configuration can be programmed through the IOCONFIG
block for each GPIO pin.
Rev. 00.11 — 13 November 2009
LPC1111/12/13/14
© NXP B.V. 2009. All rights reserved.
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