DK-DEV-5M570ZN Altera, DK-DEV-5M570ZN Datasheet - Page 17

• Manufacturer Part Number: DK-DEV-5M570ZN
• Description: KIT DEV MAX V 5M570Z
• Manufacturer: Altera
• Series: MAX® Vr
• Type: CPLDr

Specifications of DK-DEV-5M570ZN

• Contents: Board, Cable(s), Software and Documentation
• Silicon Manufacturer: Altera
• Core Architecture: CPLD
• Core Sub-architecture: MAX
• Silicon Core Number: 5M
• Silicon Family Name: MAX V
• Kit Contents: MAX V CPLD Development Board, USB Cable
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: 5M570ZF256
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2722

Chapter 3: DC and Switching Characteristics for MAX V Devices
Timing Model and Specifications
Table 3–24. UFM Block Internal Timing Microparameters for MAX V Devices (Part 3 of 3)
Figure 3–3. UFM Read Waveform
January 2011 Altera Corporation
t
t
t
RA
OSCS
OSCH
Symbol
Maximum read access
time
Maximum delay between
the OSC_ENA rising edge
to the erase/program
signal rising edge
Minimum delay allowed
from the
erase/program signal
going low to OSC_ENA
signal going low
OSC_ENA
Parameter
Program
DRDout
DRShft
ARShft
DRDin
ARClk
ARDin
DRClk
Erase
Figure 3–3
UFM block timing parameters listed in
Busy
t
t
ASU
ADS
through
t
ACLK
Min
250
250
—
9 Address Bits
5M40Z/ 5M80Z/ 5M160Z/
Figure 3–5
C4
5M240Z/ 5M570Z
Max
65
—
—
t
t
ADH
show the read, program, and erase waveforms for
AH
t
DCO
Min
250
250
t
—
DSS
C5, I5
Table
t
DCLK
Max
65
—
—
16 Data Bits
3–24.
Min
250
250
—
t
C4
DSH
5M1270Z/ 5M2210Z
Max
65
—
—
MAX V Device Handbook
Min
250
250
—
C5, I5
Max
65
—
—
3–17
Unit
ns
ns
ns