DK-DEV-5M570ZN Altera, DK-DEV-5M570ZN Datasheet - Page 10

• Manufacturer Part Number: DK-DEV-5M570ZN
• Description: KIT DEV MAX V 5M570Z
• Manufacturer: Altera
• Series: MAX® Vr
• Type: CPLDr

Specifications of DK-DEV-5M570ZN

• Contents: Board, Cable(s), Software and Documentation
• Silicon Manufacturer: Altera
• Core Architecture: CPLD
• Core Sub-architecture: MAX
• Silicon Core Number: 5M
• Silicon Family Name: MAX V
• Kit Contents: MAX V CPLD Development Board, USB Cable
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: 5M570ZF256
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2722

3–10
Timing Model and Specifications
Figure 3–2. Timing Model for MAX V Devices
MAX V Device Handbook
I/O Pin
Preliminary and Final Timing
INPUT
I/O Input Delay
f
t
IN
MAX V devices timing can be analyzed with the Altera Quartus
of industry-standard EDA simulators and timing analyzers, or with the timing model
shown in
MAX V devices have predictable internal delays that allow you to determine the
worst-case timing of any design. The software provides timing simulation,
point-to-point delay prediction, and detailed timing analysis for device-wide
performance evaluation.
You can derive the timing characteristics of any signal path from the timing model
and parameters of a particular device. You can calculate external timing parameters,
which represent pin-to-pin timing delays, as the sum of the internal parameters.
For more information, refer to
This section describes the performance, internal, external, and UFM timing
specifications. All specifications are representative of the worst-case supply voltage
and junction temperature conditions.
Timing models can have either preliminary or final status. The Quartus II software
issues an informational message during the design compilation if the timing models
are preliminary.
Preliminary status means the timing model is subject to change. Initially, timing
numbers are created using simulation results, process data, and other known
parameters. These tests are used to make the preliminary numbers as close to the
actual timing parameters as possible.
Input Routing
Global Input Delay
Memory
Delay
Flash
User
t
DL
t
GLOB
Figure
Data-In/LUT Chain
Table 3–16
3–2.
To Adjacent LE
Register Control
LUT Delay
t
Logic Element
Delay
LUT
t
C
t
R4
lists the status of the MAX V device timing models.
AN629: Understanding Timing in Altera
t
COMB
t
t
t
t
PRE
CLR
CO
SU
t
H
Register Delays
Chapter 3: DC and Switching Characteristics for MAX V Devices
t
C4
Data-Out
Combinational Path Delay
From Adjacent LE
Output Routing
t
Delay
FASTIO
t
IODR
t
IOE
January 2011 Altera Corporation
Output and Output Enable
Timing Model and Specifications
®
II software, a variety
Data Delay
Output
Delay
t
t
t
OD
XZ
ZX
CPLDs.
I/O Pin