EVAL-ADF4360-8EBZ1 Analog Devices Inc, EVAL-ADF4360-8EBZ1 Datasheet - Page 12

BOARD EVALUATION FOR ADF4360-8

EVAL-ADF4360-8EBZ1

Manufacturer Part Number
EVAL-ADF4360-8EBZ1
Description
BOARD EVALUATION FOR ADF4360-8
Manufacturer
Analog Devices Inc
Datasheet

Specifications of EVAL-ADF4360-8EBZ1

Main Purpose
Timing, Frequency Synthesizer
Embedded
No
Utilized Ic / Part
ADF4360-8
Primary Attributes
Single Integer-N PLL with VCO
Secondary Attributes
120MHz, 1MHz PFD
Silicon Manufacturer
Analog Devices
Application Sub Type
Integer-N Synthesizer
Kit Application Type
Clock & Timing
Silicon Core Number
ADF4360-8
Kit Contents
Board
Frequency
400MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q4990657
ADF4360-8
OUTPUT STAGE
The RF
connected to the collectors of an NPN differential pair driven
by buffered outputs of the VCO, as shown in Figure 20. To allow
the user to optimize the power dissipation vs. the output power
requirements, the tail current of the differential pair is pro-
grammable via Bits PL1 and PL2 in the control latch. Four cur-
rent levels may be set: 3.5 mA, 5 mA, 7.5 mA, and 11 mA. These
levels give output power levels of −9 dBm, −6 dBm, −3 dBm,
and 0 dBm, respectively, using the correct shunt inductor to V
and ac coupling into a 50 Ω load. Alternatively, both outputs can
be combined in a 1 + 1:1 transformer or a 180° microstrip cou-
pler (see the Output Matching section).
OUT
A and RF
OUT
B pins of the ADF4360 family are
Rev. A | Page 12 of 24
DD
If the outputs are used individually, the optimum output stage
consists of a shunt inductor to V
Another feature of the ADF4360 family is that the supply current
to the RF output stage is shut down until the part achieves lock, as
measured by the digital lock detect circuitry. This is enabled by the
Mute-Till-Lock Detect (MTLD) bit in the control latch.
VCO
Figure 20. Output Stage ADF4360-8
BUFFER
DD
RF
.
OUT
A
RF
OUT
B

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