IDTTSE2002B3CNRG IDT, Integrated Device Technology Inc, IDTTSE2002B3CNRG Datasheet - Page 26

• Manufacturer Part Number: IDTTSE2002B3CNRG
• Description: IC TEMP SENS EEPROM DFN-8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDTTSE2002B3CNRG

• Function: Temp Monitoring System (Sensor)
• Topology: ADC (Sigma Delta), Control Logic, Register Bank
• Sensor Type: Internal
• Sensing Temperature: -20°C ~ 125°C
• Output Type: 2-Wire Serial, I²C™/SMBUS™
• Output Alarm: No
• Output Fan: No
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -20°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-VFDFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Temperature Register Value Definitions
format. Bits B 12 through B2 for each of these registers are defined for all device resolutions as defined in the TRES field of the Capabilities Register,
hence a 0.25°C minimum granularity is supported in all registers. Examples of valid settings and interpretation of temperature register bits:
affects only the Temperature Data Register but none of the Limit Registers. When higher resolution devices generate status or EVENT changes, only
bits B12 through B2 are used in the comparison; however, all 11 bits (TRES[1-0] = 10) or all 12 bits (TRES[1-0] = 11) are visible in reads from the
Temperature Data Register.
detected, bit 2 of all Limit Registers should be programmed to 0 to assure correct operation of the temperature comparators.
High Limit Register
temperature status and thermal EVENTs. For future compatibility, unused bits “-” must be programmed as 0.
High Limit Register
equal to the High Limit, then the EVENT pin is asserted (if enabled). If the EVENT_LOCK bit is set as shown in the Configuration Register table), then
this register becomes read-only.
Temperature Register Coding Examples
xxx0 0000 0010 11xx
xxx0 0000 0001 00xx
xxx0 0000 0000 01xx
xxx0 0000 0000 00xx
xxx1 1111 1111 11xx
xxx1 1111 1111 00xx
xxx1 1111 1101 01xx
ADDR R/W
Bit 0 – EVENT_MODE; Controls the behavior of the EVENT pin. The EVENT pin may function in either comparator or interrupt mode.
Temperatures in the High Limit Register, Low Limit Register, TCRIT Register, and Temperature Data Register are expressed in two's complement
The TRES field of the Capabilities Register optionally defines higher resolution devices. For compatibility and simplicity, this additional resolution
When a lower resolution device is indicated in the Capabilities Register (TRES[1-0] = 00), the finest resolution supported is 0.5°C. When this is
The temperature limit registers (High, Low, and TCRIT) define the temperatures to be used by various on-chip comparators to determine device
The High Limit Register holds the High Limit for the nominal operating window. When the temperature rises above the High Limit, or drops below or
02
B15~B0 (binary)
'0' (default); The EVENT pin is active low. The “active” state of the pin will be logical '0'.
'1'; The EVENT pin is active high. The “active” state of the pin will be logical '1'.
'0'; The EVENT pin will function in comparator mode.
'1'; The EVENT pin will function in interrupt mode.
R/W
B15/B7
–
8
B14/B6
–
4
Value
+2.75
+1.00
+0.25
-0.25
-1.00
-2.75
0
B13/B5
–
2
Units
°C
°C
°C
°C
°C
°C
°C
B12/B4
Sign
1
26 of 30
B11/B3
128
0.5
B10/B2
0.25
64
B9/B1
32
–
B8/B0
16
–
May 12, 2010
Default
0000