MC13783VK5 Freescale Semiconductor, MC13783VK5 Datasheet - Page 28

• Manufacturer Part Number: MC13783VK5
• Description: IC PWR MNGMNT ATLAS 3G 247MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC13783VK5

• Applications: Handheld/Mobile Devices
• Operating Temperature: -30°C ~ 85°C
• Mounting Type: *
• Package / Case: 247-MAPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Voltage - Supply: -

Functional Description
4.3.2.3
In master mode the CLI is divided internally to generate the BCL and FS signals. In slave mode these
clocks have to be supplied and in that case there is no imposed relationship between BCL and the other
clocks as long as it is high enough to support the number of time slots requested. The supported clock rates
are 13.0 MHz, 15.36 MHz, 16.8 MHz, 26.0 MHz and 33.6 MHz.
4.3.3
4.3.3.1
The stereo DAC is based on a 16-bit linear left and right channel D/A converter with integrated filtering.
28
Peak Output (+3 dBm0) single ended output
CODEC PSRR
Total Distortion
(noise and harmonic)
Idle Channel Noise
Inband Spurious
Absolute Gain
L/R Gain
Mismatch
Dynamic Range
Output PSRR
Spurious
Stereo DAC
Parameter
Parameter
Clock Modes
D/A Converter
Table 13. Telephone CODEC D/A Performance Specifications
Table 14. Stereo DAC Main Performance Specifications
Input at 0 dBFS,
from 20 Hz to 20 kHz
Input at -3 dBFS, 1.02 kHz
(SNDR at -60 dBFS and 1.02 kHz) + 60 dB,
20 kHz BW out,
A weighted
with respect to battery,
input at 0 dBFS,
from 20 Hz to 20 kHz
A weighted
input at -3 dBFS,
from 20 Hz to 20 kHz,
20 kHz BW out
Includes idle tones
with respect to B+,
20 Hz to 20 kHz,
at 1.02 kHz, 0 dBm0,
20 kHz measurement BW out
at CODEC output,
BW out = 20 kHz A weighted
0 dBm0 at 1.02 kHz to 3.4 kHz input.
300 Hz to 20.0 kHz
MC13783 Technical Data, Rev. 3.5
Condition
Condition
REFC - 1
Min
80
65
—
—
Min
-0.5
92
90
—
—
Typ
Typ
-78
0.2
96
90
75
—
—
—
—
REFC + 1
Max
+0.5
-75
0.3
—
—
Max
-74
-50
Freescale Semiconductor
—
—
Units
dB
dB
dB
dB
dB
dBm0
Units
dB
dB
dB
V