MC13783VK5 Freescale Semiconductor, MC13783VK5 Datasheet - Page 19

• Manufacturer Part Number: MC13783VK5
• Description: IC PWR MNGMNT ATLAS 3G 247MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC13783VK5

• Applications: Handheld/Mobile Devices
• Operating Temperature: -30°C ~ 85°C
• Mounting Type: *
• Package / Case: 247-MAPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Voltage - Supply: -

The default CS polarity is active high. The CS line must remain active during the entire SPI transfer. In
case the CS line goes inactive during a SPI transfer all data is ignored. To start a new SPI transfer, the CS
line must go inactive and then go active again. The MISO line will be tri-stated while CS is low.
Note that not all bits are truly writable. Refer to the individual subcircuit descriptions to determine the
read/write capability of each bit. All unused SPI bits in each register must be written to a zero. SPI
readbacks of the address field and unused bits are returned as zero. To read a field of data, the MISO pin
will output the data field pointed to by the 6 address bits loaded at the beginning of the SPI sequence.
4.1.1.3.2
The requirements for both SPI interfaces are equivalent. Therefore, all SPI bus names without prefix PRI
or SEC correspond to both SPI interfaces. The below diagram and table summarize the SPI electrical and
timing requirements. The SPI input and output levels are set independently via the PRIVCC and SECVCC
pins by connecting those to the proper supply.
Freescale Semiconductor
CS
CLK
MOSI
MISO
CS
MOSI
MISO
Write_En
SPI Requirements
Address5
Figure 3. SPI Transfer Protocol Multiple Read/Write Access
Preamble
Figure 2. SPI Transfer Protocol Single Read/Write Access
Address4
Address3
24 Bits Data
24 Bits Data
First Address
MC13783 Technical Data, Rev. 3.5
Address2
Address 1
Address 0
Preamble
“Dead Bit”
24 Bits Data
Another Address
24 Bits Data
Data 23
Data 23
Data 22
Data 22
Data 1
Data 1
Functional Description
Data 0
Data 0
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