FAN73933MX Fairchild Semiconductor, FAN73933MX Datasheet
FAN73933MX
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FAN73933MX Summary of contents
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... Motor Drive Inverter Ordering Information Part Number FAN73933M 14-Lead, Small Outline Integrated Circuit (SOIC), Non-JEDEC, .150 FAN73933MX Inch Narrow Body, 225SOP For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. © 2009 Fairchild Semiconductor Corporation FAN73933 • Rev. 1.0.0 Description ...
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... Typical Application Diagrams +15V Controller HIN LIN Internal Block Diagram HIN 1 250K SCHMITT TRIGGER INPUT LIN 2 SHOOT THOUGH 250K PREVENTION R DTINT DT 4 DEAD-TIME { DTMIN=220ns } Pin and 14 are no connection © 2009 Fairchild Semiconductor Corporation FAN73933 • Rev. 1.0 BOOT BOOT FAN73933 HIN LIN ...
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... Pin Configuration Pin Definitions Pin # Name 1 HIN 2 LIN COM © 2009 Fairchild Semiconductor Corporation FAN73933 • Rev. 1.0.0 HIN LIN COM Figure 3. Pin Configurations (Top View) Description Logic Input for High-Side Gate Driver Output Logic Input for Low-Side Gate Driver Output ...
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... Low-Side Output Voltage LO V Logic Input Voltage (HIN and LIN Programmable Dead-Time Pin Voltage V Logic Ground SS T Operating Ambient Temperature A © 2009 Fairchild Semiconductor Corporation FAN73933 • Rev. 1.0.0 =25°C unless otherwise specified. A Characteristics ( under any circumstances. Parameter 4 Min. Max. Unit -0.3 625 ...
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... Output Low, Short-Circuit Pulsed Current O- Allowable Negative Propagation to HO Note: 4. These parameters guaranteed by design. © 2009 Fairchild Semiconductor Corporation FAN73933 • Rev. 1.0.0 and T = 25°C, unless otherwise specified. The /COM and are applicable to the respective input leads: HIN and LIN. The V Test Condition ...
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... Turn-Off Fall Time F Dead Time: LO Turn-Off to HO Turn-On & Turn-Off to LO Turn-On MDT Dead-Time Matching=|DT Note: 5 The turn-on propagation display does not include dead time. © 2009 Fairchild Semiconductor Corporation FAN73933 • Rev. 1.0.0 =1000pF, DT=V and T =25°C, unless otherwise specified Conditions (5) ...
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... Temperature [°C] Figure 6. Turn-On Rise Time vs. Temperature 300 250 200 150 -40 - Temperature [°C] Figure 8. Dead Time (R =0Ω) vs. Temperature DT © 2009 Fairchild Semiconductor Corporation FAN73933 • Rev. 1.0.0 230 210 190 170 150 130 High-Side 110 Low-Side 90 -40 - 100 120 Figure 5 ...
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... Temperature [°C] Figure 12. Delay Matching vs. Temperature 1500 1300 1100 900 700 500 300 -40 - Temperature [°C] Figure 14. Quiescent V DD vs. Temperature © 2009 Fairchild Semiconductor Corporation FAN73933 • Rev. 1.0.0 (Continued DT1 DT2 Ω (R =300K ) 100 120 Figure 11. Dead Time Matching (R 600 ...
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... Temperature [°C] Figure 18. V UVLO+ vs. Temperature DD 10.0 9.5 9.0 8.5 8.0 -40 - Temperature [°C] Figure 20. V UVLO+ vs. Temperature BS © 2009 Fairchild Semiconductor Corporation FAN73933 • Rev. 1.0.0 (Continued) 800 700 600 500 400 300 200 100 - 100 120 Supply Current Figure 17. Operating V 9 ...
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... Temperature [°C] Figure 24. Logic High Input Voltage vs. Temperature -40 - Temperature [°C] Figure 26. Logic Input High Bias Current vs. Temperature © 2009 Fairchild Semiconductor Corporation FAN73933 • Rev. 1.0.0 (Continued) 0.4 High-Side Low-Side 0.2 0.0 -0.2 -0.4 - 100 120 Figure 23. Low-Level Output Voltage 3.0 ...
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... Supply Voltage [V] Figure 30. Turn-On Rise Time vs. Supply Voltage 1500 1300 1100 900 700 500 300 Supply Voltage [V] Figure 32. Quiescent V DD vs. Supply Voltage © 2009 Fairchild Semiconductor Corporation FAN73933 • Rev. 1.0.0 (Continued) 230 210 190 170 150 130 High-Side 110 Low-Side Figure 29 ...
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... Typical Characteristics 2.0 1.5 1.0 0.5 0 Supply Voltage [V] Figure 34. High-Level Output Voltage vs. Supply Voltage © 2009 Fairchild Semiconductor Corporation FAN73933 • Rev. 1.0.0 (Continued) 0.4 High-Side Low-Side 0.2 0.0 -0.2 -0 Figure 35. Low-Level Output Voltage 12 High-Side Low-Side Supply Voltage [V] vs. Supply Voltage ...
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... Switching Time Definitions LO +15V μ 10 LIN HIN LO HO LIN 50% More than dead-time HIN t OFF 90 © 2009 Fairchild Semiconductor Corporation FAN73933 • Rev. 1.0.0 HIN HIN LIN 2 13 LIN μ COM 1nF 100nF Figure 36. Switching Time Test Circuit Shoot Though Prevent DT DT Figure 37 ...
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... S GND Figure 40. V Waveforms During Q1 Turn-Off S © 2009 Fairchild Semiconductor Corporation FAN73933 • Rev. 1.0.0 Figure 41. and Figure 42. show the commutation of the load current between the high-side switch, Q1, and low- side freewheelling diode, D3, in same inverter leg. The parasitic inductances in the inverter circuit from the die ...
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... To reduce the EM coupling and improve the power switch turn-on/off performance, the gate drive loops must be reduced as much as possible. © 2009 Fairchild Semiconductor Corporation FAN73933 • Rev. 1.0.0 transient performance Placement of Components S The recommended selection of component is as follows: Place a bypass capacitor between the V pins. A ceramic 1µ ...
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... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’ ...
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... Fairchild Semiconductor Corporation FAN73933 • Rev. 1.0.0 17 www.fairchildsemi.com ...