PCF85176T/1,118 NXP Semiconductors, PCF85176T/1,118 Datasheet - Page 29

• Manufacturer Part Number: PCF85176T/1,118
• Description: IC LCD DISPLAY DVR 40SEG 56TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCF85176T/1,118

• Package / Case: 56-TFSOP (0.240", 6.10mm Width)
• Display Type: LCD
• Configuration: 40 Segment
• Interface: I²C
• Current - Supply: 20µA
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Digits: 20
• Number Of Segments: 40
• Maximum Clock Frequency: 2640 Hz
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Power Dissipation: 400 mW
• Maximum Operating Temperature: + 95 C
• Attached Touch Screen: No
• Maximum Supply Current: 20 uA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Digits Or Characters: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-5933-2; PCF85176T/1,118

NXP Semiconductors
11. Dynamic characteristics
Table 17.
V
[1]
[2]
[3]
PCF85176_1
Product data sheet
Symbol
Clock
f
f
f
t
t
Synchronization
t
t
t
I
Pin SCL
f
t
t
Pin SDA
t
t
Pins SCL and SDA
t
t
t
t
t
t
C
t
clk(int)
clk(ext)
fr
clk(H)
clk(L)
PD(SYNC_N)
SYNC_NL
PD(drv)
2
SCL
LOW
HIGH
SU;DAT
HD;DAT
BUF
SU;STO
HD;STA
SU;STA
r
f
w(spike)
DD
C-bus
b
= 1.8 V to 5.5 V; V
Typical output duty factor: 50 % measured at the CLK output pin.
Not tested in production.
All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to V
input voltage swing of V
[3]
Dynamic characteristics
Parameter
internal clock frequency
external clock frequency
frame frequency
HIGH-level clock time
LOW-level clock time
SYNC propagation delay
SYNC LOW time
driver propagation delay
SCL clock frequency
LOW period of the SCL clock
HIGH period of the SCL clock
data set-up time
data hold time
bus free time between a STOP and
START condition
set-up time for STOP condition
hold time (repeated) START condition
set-up time for a repeated START
condition
rise time of both SDA and SCL signals f
fall time of both SDA and SCL signals
capacitive load for each bus line
spike pulse width
SS
SS
= 0 V; V
to V
DD
LCD
.
= 2.5 V to 6.5 V; T
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 14 April 2010
Conditions
internal clock
external clock
V
f
on the I
SCL
SCL
LCD
amb
= 400 kHz
< 125 kHz
= 5 V
=
2
−
C-bus
40
°
C to +85
[1]
[2]
Universal LCD driver for low multiplex rates
°
C; unless otherwise specified.
Min
1440
960
60
40
60
60
-
1
-
-
1.3
0.6
100
0
1.3
0.6
0.6
0.6
-
-
-
-
-
Typ
1970
-
82
-
-
-
30
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PCF85176
Max
2640
2640
110
110
-
-
-
-
30
400
-
-
-
-
-
-
-
-
0.3
400
50
0.3
1.0
© NXP B.V. 2010. All rights reserved.
IL
and V
IH
Unit
Hz
Hz
Hz
Hz
μs
μs
ns
μs
μs
kHz
μs
μs
ns
ns
μs
μs
μs
μs
μs
μs
μs
pF
ns
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