PCF85176T/1,118 NXP Semiconductors, PCF85176T/1,118 Datasheet - Page 27

IC LCD DISPLAY DVR 40SEG 56TSSOP

PCF85176T/1,118

Manufacturer Part Number
PCF85176T/1,118
Description
IC LCD DISPLAY DVR 40SEG 56TSSOP
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PCF85176T/1,118

Package / Case
56-TFSOP (0.240", 6.10mm Width)
Display Type
LCD
Configuration
40 Segment
Interface
I²C
Current - Supply
20µA
Voltage - Supply
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Number Of Digits
20
Number Of Segments
40
Maximum Clock Frequency
2640 Hz
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Power Dissipation
400 mW
Maximum Operating Temperature
+ 95 C
Attached Touch Screen
No
Maximum Supply Current
20 uA
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Digits Or Characters
-
Lead Free Status / Rohs Status
 Details
Other names
568-5933-2
PCF85176T/1,118

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PCF85176T/1,118
Manufacturer:
NXP/恩智浦
Quantity:
20 000
NXP Semiconductors
10. Static characteristics
Table 16.
V
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
PCF85176_1
Product data sheet
Symbol
Supplies
V
V
I
I
Logic
V
V
V
I
I
I
I
C
LCD outputs
ΔV
R
DD
DD(LCD)
OL
OH(CLK)
L
L(OSC)
DD
DD
LCD
P(POR)
IL
IH
I
O
O
= 1.8 V to 5.5 V; V
V
LCD outputs are open-circuit; inputs at V
For typical values, see
For typical values, see
When tested, I
as well).
Propagation delay of driver between clock (CLK) and LCD driving signals.
Periodically sampled, not 100 % tested.
Outputs measured one at a time.
LCD
> 3 V for
Static characteristics
Parameter
supply voltage
LCD supply voltage
supply current
LCD supply current
power-on reset supply voltage
LOW-level input voltage
HIGH-level input voltage
LOW-level output current
HIGH-level output current on pin CLK
leakage current
leakage current on pin OSC
input capacitance
output voltage variation
output resistance
1
2
C pins SCL and SDA have no diode to V
3
bias.
SS
Figure
Figure
= 0 V; V
19.
20.
LCD
= 2.5 V to 6.5 V; T
SS
All information provided in this document is subject to legal disclaimers.
or V
DD
; external clock with 50 % duty factor; I
Rev. 01 — 14 April 2010
Conditions
f
f
on pins CLK, SYNC,
OSC, A0 to A2, SA0,
SCL, SDA
on pins CLK, SYNC,
OSC, A0 to A2, SA0,
SCL, SDA
output sink current;
V
output source current;
V
V
on pins CLK, SCL, SDA,
A0 to A2 and SA0
V
on pins BP0 to BP3 and
S0 to S39
V
clk(ext)
clk(ext)
DD
OL
OH
I
I
LCD
on pins CLK and SYNC
on pin SDA
on pins BP0 to BP3
on pins S0 to S39
amb
= V
= V
and may be driven to the V
= 0.4 V; V
= 4.6 V; V
= 5 V
DD
DD
=
= 1536 Hz
= 1536 Hz
or V
40
°
SS
C to +85
DD
DD
;
= 5 V
= 5 V
Universal LCD driver for low multiplex rates
°
C; unless otherwise specified.
I
[1]
[2][3]
[2][4]
[5][6]
[7]
[8]
limiting values given in
2
C-bus inactive.
Min
1.8
2.5
-
-
1.0
V
0.7V
1
3
1
−1
−1
-
−100
-
-
SS
DD
Typ
-
-
-
-
1.3
-
-
-
-
-
-
-
-
-
1.5
6.0
PCF85176
Table 15
© NXP B.V. 2010. All rights reserved.
Max
5.5
6.5
20
60
1.6
0.3V
V
-
-
-
+1
+1
7
+100
-
-
DD
(see
DD
Figure 18
27 of 43
Unit
V
V
μA
μA
V
V
V
mA
mA
mA
μA
μA
pF
mV

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