RC28F256P33TFA NUMONYX, RC28F256P33TFA Datasheet - Page 43

• Manufacturer Part Number: RC28F256P33TFA
• Description: IC FLASH 256MBIT 95NS 64EZBGA
• Manufacturer: NUMONYX
• Series: Axcell™r

Specifications of RC28F256P33TFA

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 256M (16Mx16)
• Speed: 95ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-EZBGA
• Cell Type: NOR
• Density: 256Mb
• Interface Type: Parallel/Serial
• Boot Type: Top
• Address Bus: 25b
• Operating Supply Voltage (typ): 2.5/3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: EZBGA
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 32M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 902063; 902063; RC28F256P33TF 902063

P33-65nm
12.0
12.1
12.2
Table 16: Power and Reset
Datasheet
43
Notes:
1.
2.
3.
4.
5.
6.
7.
Num
P1
P2
P3
t
t
t
These specifications are valid for all device versions (packages and speeds).
The device may reset if t
Not applicable if RST# is tied to VCC.
Sampled, but not 100% tested.
When RST# is tied to the VCC supply, device will not be ready until t
When RST# is tied to the VCCQ supply, device will not be ready until t
Reset completes within t
Symbol
PLPH
PLRH
VCCPH
Power and Reset Specifications
Power-Up and Power-Down
Power supply sequencing is not required if VPP is connected to VCC or VCCQ. Otherwise
VCC and VCCQ should attain their minimum operating voltage before applying VPP.
Power supply transitions should only occur when RST# is low. This protects the device
from accidental programming or erasure during power transitions.
Reset Specifications
Asserting RST# during a system reset is important with automated program/erase
devices because systems typically expect to read from flash memory when coming out
of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization
may not occur. This is because the flash memory may be providing status information,
instead of array data as expected. Connect RST# to the same active low reset signal
used for CPU initialization.
Also, because the device is disabled when RST# is asserted, it ignores its control inputs
during power-up/down. Invalid bus conditions are masked, providing a level of memory
protection.
RST# pulse width low
RST# low to device reset during erase
RST# low to device reset during program
VCC Power valid to RST# de-assertion (high)
PLPH
PLPH
if RST# is asserted while no erase or program operation is executing.
is < t
Parameter
PLPH
Min, but this is not guaranteed.
VCCPH
VCCPH
Min
100
300
-
-
after VCC ≥ V
after VCC ≥ V
Max
25
25
-
-
CCMIN
CCMIN
.
Order Number:320003-09
.
Unit
ns
µs
1,2,3,4
1,3,4,7
1,3,4,7
1,4,5,6
Notes
Mar 2010