MPC8533EVTARJA Freescale Semiconductor, MPC8533EVTARJA Datasheet - Page 707

• Manufacturer Part Number: MPC8533EVTARJA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Consider the following SDRAM organization:
The logical address is partitioned as shown in
The following parameters are extracted:
During the address phase, the SDRAM address port is set as shown in
Because the internal bank selects are multiplexed over LA[15:16], LSDMR[BSMA] must be set to 011.
Table 14-36
Freescale Semiconductor
msb of start address
•
•
•
•
The 32-bit port size is organized as 8 × 8 × 32 Mbits.
Each device has 4 internal banks, 13 row address lines, and 10 column address lines.
COLS = 011, 10 column lines
ROWS = 100, 13 row lines
LA[0:14]
msb of start address
shows the address port configuration during a READ/WRITE command.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 14-36. SDRAM Device Address Port During READ/WRITE Command
Table 14-33. LAD n Signal Connections to 128-Mbyte SDRAM (continued)
A[0:4]
LA[0:14]
Table 14-35. SDRAM Device Address Port During Address Phase
—
Internal bank select
LA[15:16]
LAD (Latch Address)
Table 14-34. Logical Address Bus Partitioning
LAD19 (no connect)
Internal bank select A[18:19]
A[5:17]
Row
LAD21
LAD20
LAD18
LAD17
LAD16
LAD15
LA[15:16]
LA[17:18]
Don’t care
Table
Bank select
A[18:19]
BA0 (if LSDMR[BSMA] = 011)
BA1 (if LSDMR[BSMA] = 011)
A10 is connected to LSDA10
14-34.
SDRAM Address Signal
A11
A12
Row A[5:17]
A8
A9
LA[19]
LA[17:29]
AP
A[20:29]
Column
Table
14-35.
LA[20:29]
Column
No connect
LA[30:31]
A[30:31]
lsb
Local Bus Controller
No connect
LA[30:31]
14-89