MPC8533EVTARJA Freescale Semiconductor, MPC8533EVTARJA Datasheet - Page 626

• Manufacturer Part Number: MPC8533EVTARJA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Local Bus Controller
14.3
Table 14-3
a cross-reference to the complete description of each register. Note that the full register address is
comprised of CCSRBAR together with the block base address and offset listed in
4-byte address spaces within offset 0x000–0xFFF are reserved.
In this table and in the register figures and field descriptions, the following access definitions apply:
14-8
LSYNC_OUT
MSRCID[0:4]
LSYNC_IN
LCLK[0:2]
MDVAL
•
•
Signal
Reserved fields are always ignored for the purposes of determining access type.
R/W, R, and W (read/write, read only, and write only) indicate that all the non-reserved fields in a
register have the same access type.
Memory Map/Register Definition
shows the memory mapped registers of the LBC and their offsets. It lists the offset, name, and
I/O
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
O Local bus clocks
O PLL synchronization out
O Local bus data valid (LBC debug mode only)
O Local bus source ID (LBC debug mode only). In debug mode, all MSRCID[0:4] signals are driven high
I PLL synchronization in
Table 14-2. Local Bus Controller Detailed Signal Descriptions (continued)
unless MSRCID[0:4] is driving a debug source ID for identifying the internal system device controlling the
LBC.
Meaning
Meaning
Meaning
Meaning
Meaning
Timing Assertion/Negation—The time delay of the timing loop should be such that it compensates for
Timing Assertion/Negation—Valid only while the LBC is in system debug mode. In debug mode, MDVAL
State
State
State
State
State
Asserted/Negated—LCLK[0:2] drive an identical bus clock signal for distributed loads. If the LBC
Asserted/Negated—A replica of the bus clock, appearing on LSYNC_OUT, should be
Asserted/Negated—See description of LSYNC_OUT.
Asserted/Negated—For a read, MDVAL asserts for one bus cycle in the cycle immediately
Asserted/Negated—Remain high until the last bus cycle of the assertion of LALE, in which case
PLL is enabled (see LCRR[PBYP],
shifted earlier than transitions on other LBC signals (such as LAD[0:31] and LCS n ) by a
time delay matching the delay of the PLL timing loop set up between LSYNC_OUT and
LSYNC_IN.
propagated through a passive timing loop and returned to LSYNC_IN for achieving correct
PLL lock.
the round-trip flight time of LCLK[2] and clocked drivers in the system. No load other than
a timing loop should be placed on LSYNC_OUT.
preceding the sampling of read data on LAD[0:31]. For a write, MDVAL asserts for one bus
cycle during the final cycle for which the current write data on LAD[0:31] is valid. During
burst transfers, MDVAL asserts for each data beat.
asserts when the LBC generates a data transfer acknowledge.
the source ID of the address is indicated, or until MDVAL is asserted, in which case the
source ID relating to the data transfer is indicated. In case of address debug, MSRCID[0:4]
is valid only when the address on LAD[0:31] consists of all physical address bits—with
optional padding—for reconstructing the system address presented to the LBC. For
example, MSRCID[0:4] is valid only during CAS phases of SDRAM accesses, because the
column, bank select, and (normally unused) row address bits are all present on LAD[0:31]
during a CAS cycle
Description
Figure 14-19 on page
14-30), the bus clock phase is
Table
Freescale Semiconductor
14-3. Undefined