MPC8533EVTARJA Freescale Semiconductor, MPC8533EVTARJA Datasheet - Page 1302

• Manufacturer Part Number: MPC8533EVTARJA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Glossary
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Glossary-4
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Implementation. A particular processor that conforms to the architecture, but may differ
Inbound ATMU windows. Mappings that perform address translation from the external
In-order. An aspect of an operation that adheres to a sequential model. An operation is
Integer unit. An execution unit in the core responsible for executing integer instructions.
Inter-packet gap. The gap between the end of one Ethernet packet and the beginning of
Instruction latency. The total number of clock cycles necessary to execute an instruction
Kill. An operation that causes a
L2 cache. Level-2 cache. See
Latency. The number of clock cycles necessary to execute an instruction and make ready
Least-significant bit (lsb). The bit of least value in an address, register, field, data
Least-significant byte (LSB). The byte of least value in an address, register, data element,
Little-endian. A byte-ordering method in memory where the address n of a word
Local access window. Mapping used to translate a region of memory to a particular target
Media access control (MAC) sublayer. Sublayer that provides a logical connection
from other architecture-compliant implementations for example in design, feature
set, and implementation of optional features.
address space to the local address space, attach attributes and transaction types to
the transaction, and map the transaction to its target interface.
said to be performed in-order if, at the time that it is performed, it is known to be
required by the sequential execution model.
the next transmitted packet.
and make ready the results of that instruction.
data to memory.
the results of that execution for a subsequent instruction.
element, or instruction encoding.
or instruction encoding.
corresponds to the least-significant byte. In an addressed memory word, the bytes
are ordered (left to right) 3, 2, 1, 0, with 3 being the most-significant byte. See
endian.
interface, such as the DDR SDRAM controller or the PCI controller. The local
memory map is defined by a set of eight local access windows. The size of each
window can be configured from 4 Kbytes to 2 Gbytes.
between the MAC and its peer station. Its primary responsibility is to initialize,
control, and manage the connection with the peer station.
Secondary
cache block
cache.
to be invalidated without writing any modified
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