MPC8533EVTARJA Freescale Semiconductor, MPC8533EVTARJA Datasheet - Page 1185

no-image

MPC8533EVTARJA

Manufacturer Part Number
MPC8533EVTARJA
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8533EVTARJA

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
1.067GHz
Voltage
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Package / Case
783-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8533EVTARJA
Manufacturer:
FREESCAL
Quantity:
156
Part Number:
MPC8533EVTARJA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
19.4.1.25 SerDes 2 Control Register 1 (SRDS2CR1)
Shown in
of the SerDes 2 signals. Note that reserved fields with non-zero reset values are for internal use only and
their values should be preserved.
Table 19-28
19.5
This section describes the global utilities from a functional perspective.
19.5.1
The MPC8533E has features to minimize power consumption at several levels. Dynamic power
management locally minimizes power consumption when a block is idle. Software can also shut down
clocks to individual blocks when they are not needed through a memory-mapped register (DEVDISR).
Additionally, software running on the e500 core can access the core’s SPRs to put the device into doze,
nap, or sleep power down state. Finally, software can access a memory-mapped register (POWMGTCR)
in the global utilities block to put the device in the doze or sleep states.
Freescale Semiconductor
Offset 0xE_0F10
Reset 0 0 0 1 0 0
16–19
20–31
0–15
Bits
W
R
0
Figure
Functional Description
Power Management
describes the bit settings of SRDS2CR1.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
XMITEQA
19-25, SRDS2CR1 contains the control bits used for adjusting the transmit equalization
Name
Figure 19-25. SerDes 2 Control Register 1 (SRDS2CR1)
0
Reserved
Transmit equalization selection bus for SerDes 2 lane a (SD2_RX0/TX0)
Default value = 4’b0100
MSB (bit 16) is the differential peak-to-peak amplitude selection:
0 = Vdd-diff-pk=pk
1 = 5/6 Vdd-diff-pk=pk
LSBs (bits 17:19) are the equalization amplitude selection:
000 = No equalization
001 = 1.09x relative amplitude
010 = 1.2x relative amplitude
011 = 1.33x relative amplitude
100 = 1.5x relative amplitude
101 = 1.71x relative amplitude
110 = 2.0x relative amplitude
111 = reserved
Reserved
Table 19-28. SRDS2CR1 Field Descriptions
1 0 0 0 0 0 0 0 0 0
15 16
XMITEQA
1
Description
0
19 20
0
0
1
0
0
0
0 0 1 1 0 0
Access: Read/Write
Global Utilities
19-25
31
0

Related parts for MPC8533EVTARJA