PIC16F721-I/ML Microchip Technology, PIC16F721-I/ML Datasheet - Page 9

• Manufacturer Part Number: PIC16F721-I/ML
• Description: MCU PIC 4K FLASH 20-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F721-I/ML

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 17
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-VFQFN Exposed Pad
• Controller Family/series: PIC16F
• No. Of I/o's: 18
• Ram Memory Size: 256Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.0
In Program/Verify mode, the program memory and the
configuration
programmed
ICSPCLK are used for the data and the clock,
respectively. All commands and data words are
transmitted LSb first. Data changes on the rising edge
of the ICSPCLK and latched on the falling edge. In
Program/Verify mode, both the ICSPDAT and
ICSPCLK are Schmitt Trigger inputs. The sequence
that enters the device into Program/Verify mode
places all other logic into the Reset state. Upon
entering
automatically configured as high-impedance inputs
and the address is cleared.
4.1
There are two different methods of entering Program/
Verify mode:
• V
• V
4.1.1
To enter Program/Verify mode via the V
the following sequence must be followed:
1.
2.
3.
The V
code prior to entering Program/Verify mode. For
example, when the Configuration Word has MCLR
TABLE 4-1:
 2011 Microchip Technology Inc.
Load Configuration
Load Data For Program Memory
Read Data From Program Memory
Increment Address
Reset Address
Begin Internally Timed Programming
Begin Externally Timed Programming
End Externally Timed Programming
Bulk Erase Program Memory
Row Erase Program Memory
PP
DD
Hold ICSPCLK and ICSPDAT low. All other pins
should be unpowered.
Raise the voltage on MCLR from 0V to V
Raise the voltage on V
operating voltage.
PP
– First entry mode
– First entry mode
-first entry prevents the device from executing
PROGRAM/VERIFY MODE
Program/Verify Mode Entry and
Exit
Program/Verify
V
PP
Command
in
memory
– FIRST ENTRY MODE
COMMAND MAPPING FOR PIC16F/LF720 AND PIC16F/LF721
serial
can
DD
fashion.
mode,
from 0V to the desired
be
accessed
ICSPDAT
all
PP
x
x
x
x
x
x
x
x
x
x
-first method
I/Os
Advance Information
IHH
Binary (MSb … LSb)
0
0
0
0
1
0
1
0
0
1
.
and
and
are
0
0
0
0
0
1
1
1
1
0
Mapping
0
0
1
1
1
0
0
0
0
0
disabled (MCLRE = 0), the power-up time is disabled
(PWRTE = 0), the internal oscillator is selected
(F
application, the device will execute code. Since this
may prevent entry, V
recommended. See the timing diagram in
4.1.2
To enter Program/Verify mode via the V
the following sequence must be followed:
1.
2.
3.
The V
device, when V
necessary to disconnect V
mode. See the timing diagram in
4.1.3
To exit Program/Verify mode take MCLR to V
lower (V
4.2
The PIC16F/LF720 and PIC16F/LF721 implement 10
programming commands, each six bits in length. The
commands are summarized in
Commands that have data associated with them are
specified to have a minimum delay of T
command and the data. After this delay 16 clocks are
required to either clock in or clock out the 14-bit data
word. The first clock is for the Start bit and the last clock
is for the Stop bit.
OSC
0
1
0
1
1
0
0
1
0
0
Hold ICSPCLK and ICSPDAT low.
Raise the voltage on V
operating voltage.
Raise the voltage on MCLR from V
to V
DD
= 10x), and RA0 and RA1 are driven by the user
IL
PIC16(L)F720/721
IHH
-first method is useful when programming the
Program/Verify Commands
). See Figures
0
0
0
0
0
0
0
0
1
1
.
V
PROGRAM/VERIFY MODE EXIT
DD
Hex
0Ah
DD
00h
02h
04h
06h
16h
08h
18h
09h
– FIRST ENTRY MODE
11h
is already applied, for it is not
PP
0, data (14), 0
0, data (14), 0
0, data (14), 0
Internally Timed
Internally Timed
-First Entry mode is strongly
8-3
DD
DD
and 8-4.
from 0V to the desired
to enter Program/Verify
Table
Figure
Data/Note
4-1.
DS41409B-page 9
DLY
DD
DD
8-1.
-first method,
Figure
between the
or below
DD
8-2.
or