PIC16F721-I/ML Microchip Technology, PIC16F721-I/ML Datasheet - Page 24

• Manufacturer Part Number: PIC16F721-I/ML
• Description: MCU PIC 4K FLASH 20-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F721-I/ML

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 17
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-VFQFN Exposed Pad
• Controller Family/series: PIC16F
• No. Of I/o's: 18
• Ram Memory Size: 256Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16(L)F720/721
EXAMPLE 7-2:
EXAMPLE 7-3:
DS41409B-page 24
PIC16LF720
PIC16F721
Note 1: Total number of program memory address locations: 07FFh + 1 = 0800h. Then, 0800h - 2 = 07FEh.
Note 1: Sum of Memory addresses = (Total number of program memory address locations) x (3FFFh) = F800h,
2: Configuration Word 1 and 2 = all bits are ‘1’; thus, code-protect is disabled.
3: Configuration Word 1 Mask = all Configuration Word bits are set to ‘1’, except for unimplemented bits
4: On the PIC16LF720 device, the VCAPEN bit is not implemented in Configuration Word 2; thus, all
2: Configuration Word 1 and 2 = all bits are ‘1’; thus, code-protect is disabled.
3: Configuration Word 1 and 2 Mask = all bits are set to ‘1’, except for unimplemented bits that are ‘0’.
Thus, [(07FEh x 3FFFh) + (2 x 00AAh)] = 7956h, truncated to 16 bits.
that are ‘0’.
unimplemented bits are ‘0’.
truncated to 16 bits.
Configuration Word 2 mask
Checksum
Sum of Memory addresses 0000h-07FFh
Configuration Word 1
Configuration Word 1 mask
Configuration Word 2
Sum of Memory addresses 0000h-0FFFh
Configuration Word 1
Configuration Word 1 mask
Configuration Word 2
Configuration Word 2 mask
Checksum
CHECKSUM COMPUTED WITH CODE PROTECTION DISABLED (PIC16LF720),
00AAh AT FIRST AND LAST ADDRESS
CHECKSUM COMPUTED WITH CODE PROTECTION DISABLED (PIC16F721),
BLANK DEVICE
(2)
(2)
(2)
(2)
= 7956h + (3FFFh and 337Bh) + (3FFFh and 0003h)
= 7956h + 337Bh + 0003h
= ACD4h
= F000h + (3FFFh and 337Bh) + (3FFFh and 0013h)
= F000h + 337Bh + 0013h
= 238Eh
Advance Information
(4)
(3)
(3)
(3)
(1)
(1)
7956h
3FFFh
337Bh
3FFFh
0003h
F000h
3FFFh
337Bh
3FFFh
0013h
 2011 Microchip Technology Inc.