A3PE1500-FGG676 Actel, A3PE1500-FGG676 Datasheet - Page 73

• Manufacturer Part Number: A3PE1500-FGG676
• Description: FPGA - Field Programmable Gate Array 1500K System Gates
• Manufacturer: Actel

Specifications of A3PE1500-FGG676

• Processor Series: A3PE1500
• Core: IP Core
• Maximum Operating Frequency: 231 MHz
• Number Of Programmable I/os: 444
• Data Ram Size: 276480
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 1.5 M
• Package / Case: FPBGA-676
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 2-30 • Input DDR Timing Diagram
Table 2-90 • Input DDR Propagation Delays
Out_QR
Out_QF
Parameter
t
t
t
t
t
t
t
t
t
t
t
F
Note:
DDRICLKQ1
DDRICLKQ2
DDRISUD
DDRIHD
DDRICLR2Q1
DDRICLR2Q2
DDRIREMCLR
DDRIRECCLR
DDRIWCLR
DDRICKMPWH
DDRICKMPWL
DDRIMAX
Data
CLK
CLR
For specific junction temperature and voltage supply levels, refer to
Commercial-Case Conditions: T
Timing Characteristics
Clock-to-Out Out_QR for Input DDR
Clock-to-Out Out_QF for Input DDR
Data Setup for Input DDR
Data Hold for Input DDR
Asynchronous Clear to Out Out_QR for Input DDR
Asynchronous Clear-to-Out Out_QF for Input DDR
Asynchronous Clear Removal Time for Input DDR
Asynchronous Clear Recovery Time for Input DDR
Asynchronous Clear Minimum Pulse Width for Input DDR
Clock Minimum Pulse Width High for Input DDR
Clock Minimum Pulse Width Low for Input DDR
Maximum Frequency for Input DDR
t
t
1
DDRICLR2Q1
DDRICLR2Q2
t
DDRIREMCLR
2
3
t
DDRICLKQ1
Description
J
= 70°C, Worst-Case VCC = 1.425 V
4
2
R e v i s i o n 9
3
5
t
DDRICLKQ2
t
DDRISUD
Table 2-6 on page 2-5
6
4
5
7
1404
0.39
0.27
0.28
0.00
0.57
0.46
0.00
0.22
0.22
0.36
0.32
ProASIC3E Flash Family FPGAs
–2
t
DDRIHD
1232
0.44
0.31
0.32
0.00
0.65
0.53
0.00
0.25
0.25
0.41
0.37
t
for derating values.
–1
8
DDRIRECCLR
6
7
1048
0.52
0.37
0.76
0.62
0.00
0.30
0.30
0.43
Std.
0.38
0.00
0.48
9
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2- 61