A3PE1500-FGG676 Actel, A3PE1500-FGG676 Datasheet - Page 2

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A3PE1500-FGG676

Manufacturer Part Number
A3PE1500-FGG676
Description
FPGA - Field Programmable Gate Array 1500K System Gates
Manufacturer
Actel
Datasheet

Specifications of A3PE1500-FGG676

Processor Series
A3PE1500
Core
IP Core
Maximum Operating Frequency
231 MHz
Number Of Programmable I/os
444
Data Ram Size
276480
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
1.5 M
Package / Case
FPBGA-676
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
A3PE1500-FGG676
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
A3PE1500-FGG676
Manufacturer:
MICROSEMI/美高森美
Quantity:
20 000
Part Number:
A3PE1500-FGG676I
Manufacturer:
Microsemi SoC
Quantity:
10 000
I/Os Per Package
Table 1-2 • ProASIC3E FPGAs Package Sizes Dimensions
ProASIC3E Device Status
ProASIC3E Devices
Cortex-M1 Devices
Package
PQ208
FG256
FG324
FG484
FG676
FG896
Notes:
1. When considering migrating your design to a lower- or higher-density device, refer to the
2. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
3. For A3PE1500 and A3PE3000 devices, the usage of certain I/O standards is limited as follows:
4. FG256 and FG484 are footprint-compatible packages.
5. When using voltage-referenced I/O standards, one I/O pin should be assigned as a voltage-referenced pin (V
6. "G" indicates RoHS-compliant packages. Refer to the
Package
Length × Width (mm\mm)
Nominal Area (mm
Pitch (mm)
Height (mm)
ProASIC3E Devices
A3PE600
A3PE1500
A3PE3000
ProASIC3E Flash Family FPGAs
I I
Guide
– SSTL3(I) and (II): up to 40 I/Os per north or south bank
– LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank
– SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank
(group of I/Os).
in the part number.
to ensure compliance with design and board migration requirements.
2
2
)
1
28 × 28
PQ208
3.40
784
0.5
Production
Production
Production
Status
147
165
270
A3PE600
17 × 17
FG256
1.60
289
1.0
"ProASIC3E Ordering Information" on page III
135
65
79
R ev i si o n 9
M1 ProASIC3E Devices
19 × 19
FG324
1.63
361
1.0
M1A3PE1500
M1A3PE3000
280
444
147
M1A3PE1500
A3PE1500
I/O Types
23 × 23
FG484
2.23
529
1.0
3
139
222
65
ProASIC3E FPGA Fabric User’s
27 × 27
FG676
2.23
729
1.0
for the location of the "G"
147
221
341
620
Production
Production
M1A3PE3000
A3PE3000
Status
REF
) per minibank
31 × 31
FG896
2.23
3
961
1.0
168
310
110
65

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