A3PE1500-FGG676 Actel, A3PE1500-FGG676 Datasheet - Page 23

• Manufacturer Part Number: A3PE1500-FGG676
• Description: FPGA - Field Programmable Gate Array 1500K System Gates
• Manufacturer: Actel

Specifications of A3PE1500-FGG676

• Processor Series: A3PE1500
• Core: IP Core
• Maximum Operating Frequency: 231 MHz
• Number Of Programmable I/os: 444
• Data Ram Size: 276480
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 1.5 M
• Package / Case: FPBGA-676
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the
PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output
clock in the formula by adding its corresponding contribution (P
Routing Net Contribution—P
I/O Input Buffer Contribution—P
I/O Output Buffer Contribution—P
RAM Contribution—P
PLL Contribution—P
P
P
P
P
P
NET
INPUTS
OUTPUTS
MEMORY
PLL
α
page 2-12
F
N
N
α
page 2-12
F
N
α
F
N
α
β
F
N
F
β
page 2-12
F
β
page 2-12
= P
F
= (N
CLK
CLK
CLK
CLK
READ-CLOCK
WRITE-CLOCK
CLKOUT
1
2
3
S-CELL
C-CELL
INPUTS
OUTPUTS
BLOCKS
1
1
2
2
AC13
= N
is the I/O buffer enable rate—guidelines are provided in
is the I/O buffer toggle rate—guidelines are provided in
is the I/O buffer toggle rate—guidelines are provided in
is the RAM enable rate for read operations—guidelines are provided in
is the RAM enable rate for write operations—guidelines are provided in
is the toggle rate of VersaTile outputs—guidelines are provided in
is the toggle rate of VersaTile outputs—guidelines are provided in
S-CELL
= P
= N
is the global clock signal frequency.
is the global clock signal frequency.
is the global clock signal frequency.
is the global clock signal frequency.
INPUTS
AC11
+ P
OUTPUTS
is the number of VersaTiles used as sequential modules in the design.
is the number of VersaTiles used as combinatorial modules in the design.
is the number of I/O input buffers used in the design.
is the output clock frequency.
.
.
is the number of RAM blocks used in the design.
.
.
is the number of I/O output buffers used in the design.
+ N
AC14
* N
*
is the memory read clock frequency.
C-CELL
is the memory write clock frequency.
α
PLL
BLOCKS
MEMORY
* F
2
*
/ 2 * P
α
CLKOUT
) *
2
/ 2 *
* F
α
NET
AC9
1
READ-CLOCK
β
/ 2 * P
INPUTS
* F
1
* P
OUTPUTS
CLK
AC8
AC10
R e v i s i o n 9
* F
* F
*
AC14
1
CLK
β
CLK
2
+ P
* F
CLKOUT
AC12
* N
product) to the total PLL contribution.
BLOCK
Table 2-11 on page 2-12
Table 2-11 on page 2-12
Table 2-12 on page 2-12
* F
WRITE-CLOCK
ProASIC3E Flash Family FPGAs
*
β
Table 2-11 on
Table 2-11 on
Table 2-12 on
Table 2-12 on
3
.
.
.
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