LFE2M20SE-5FN256C Lattice, LFE2M20SE-5FN256C Datasheet - Page 5
![FPGA - Field Programmable Gate Array 19K LUTs 140 I/O S-Ser SERDES DSP -5](/photos/16/14/161499/landingpagelatticeecp2m_sml.jpg)
LFE2M20SE-5FN256C
Manufacturer Part Number
LFE2M20SE-5FN256C
Description
FPGA - Field Programmable Gate Array 19K LUTs 140 I/O S-Ser SERDES DSP -5
Manufacturer
Lattice
Datasheet
1.LFE2-12SE-6FN256C.pdf
(389 pages)
Specifications of LFE2M20SE-5FN256C
Number Of Macrocells
19000
Maximum Operating Frequency
311 MHz
Number Of Programmable I/os
140
Data Ram Size
1246208
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2M20SE-5FN256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Figure 2-1. Simplified Block Diagram, ECP2-6 Device (Top Level)
sysCLOCK PLLs and DLLs
Frequency Synthesis and
Clock Alignment
Figure 2-2. Simplified Block Diagram, ECP2M20 Device (Top Level)
Configuration
Logic, Including
dual boot and encryption,
and soft-error detection
Programmable
Function Units
(PFUs)
sysDSP Blocks
Multiply and
Accumulate Support
sysMEM Block RAM
18kbit Dual Port
Flexible sysIO
Buffers:
LVCMOS, HSTL
SSTL, LVDS
Programmable
Function Units
(PFUs)
DSP Blocks
Multiply & Accumulate
Support
sysMEM Block
RAM 18kbit Dual Port
On-Chip
Oscillator
2-2
Channel
3
Channel
2
LatticeECP2/M Family Data Sheet
Channel
1
Channel
0
Flexible sysIO Buffers:
LVCMOS, HSTL, SSTL,
LVDS, and other standards
Pre-engineered source
synchronous support
• DDR1/2
• SPI4.2
• ADC/DAC devices
Flexible routing optimized
for speed, cost and routability
Configuration logic, including
dual boot and encryption.
On-chip oscillator and
soft-error detection.
Configuration port
SERDES
Pre-Engineered
Source Synchronous
Support
• DDR1/2
• SPI4.2
• ADC/DAC devices
sysCLOCK SPLLs
Flexible Routing
optimized for speed,
cost & routability
sysCLOCK GPLLs
& GDLLs
Frequency Synthesis
& Clock Alignment
Configuration Port
Architecture
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