LFE2M20SE-5FN256C Lattice, LFE2M20SE-5FN256C Datasheet - Page 146
![FPGA - Field Programmable Gate Array 19K LUTs 140 I/O S-Ser SERDES DSP -5](/photos/16/14/161499/landingpagelatticeecp2m_sml.jpg)
LFE2M20SE-5FN256C
Manufacturer Part Number
LFE2M20SE-5FN256C
Description
FPGA - Field Programmable Gate Array 19K LUTs 140 I/O S-Ser SERDES DSP -5
Manufacturer
Lattice
Datasheet
1.LFE2-12SE-6FN256C.pdf
(389 pages)
Specifications of LFE2M20SE-5FN256C
Number Of Macrocells
19000
Maximum Operating Frequency
311 MHz
Number Of Programmable I/os
140
Data Ram Size
1246208
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2M20SE-5FN256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
LFE2-20E/SE Logic Signal Connections: 256 fpBGA (Cont.)
Number
VCCIO
VCCIO
VCCIO
VCCIO
GND
GND
GND
GND
GND
Ball
H12
H13
H15
H16
H11
G16
G15
G11
G14
G13
E16
D16
D15
C15
C16
D14
B16
E13
E11
A15
E12
B15
F15
F14
F12
F16
F10
F13
F11
J13
J12
J11
F9
Ball Number
VCCIO
VCCIO
VCCIO
VCCIO
GND
GND
GND
GND
GND
H12
H13
H15
H16
H11
G16
G15
G11
G14
G13
E16
D16
D15
C15
C16
D14
B16
E13
E11
A15
E12
B15
F15
F14
F12
F16
F10
F13
F11
J13
J12
J11
F9
Ball/Pad Function
GNDIO3
GNDIO2
GNDIO2
GNDIO2
GNDIO1
VCCIO3
VCCIO2
VCCIO2
VCCIO2
PR28B
PR28A
PR27B
PR27A
PR22B
PR22A
PR21B
PR21A
PR19B
PR19A
PR17B
PR18B
PR17A
PR18A
PR16B
PR16A
PR14B
PR15B
PR14A
PR15A
PR13B
PR13A
PT64B
PT64A
PT63B
PT62B
PT63A
PR6B
PR7B
PR6A
PR7A
PR2B
PR2A
LFE2-20E/SE
4-43
Bank
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
-
-
-
-
-
RLM0_GDLLC_IN_A**/RDQ25
RLM0_GDLLT_IN_A**/RDQ25
RLM0_GDLLC_FB_A/RDQ25
RLM0_GDLLT_FB_A/RDQ25
LatticeECP2/M Family Data Sheet
PCLKC3_0/RDQ25
PCLKC2_0/RDQ16
PCLKT3_0/RDQ25
PCLKT2_0/RDQ16
VREF2_3/RDQ25
VREF1_3/RDQ25
Dual Function
VREF2_2
VREF1_2
VREF2_1
VREF1_1
RDQS16
RDQ16
RDQ16
RDQ16
RDQ16
RDQ16
RDQ16
RDQ16
RDQ16
RDQ16
RDQ16
RDQ16
RDQ8
RDQ8
RDQ8
RDQ8
Pinout Information
Differential
C (LVDS)*
T (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
T (LVDS)*
C (LVDS)*
T (LVDS)*
C (LVDS)*
T (LVDS)*
C (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
C
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
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