LFE2M20SE-5FN256C Lattice, LFE2M20SE-5FN256C Datasheet - Page 111
![FPGA - Field Programmable Gate Array 19K LUTs 140 I/O S-Ser SERDES DSP -5](/photos/16/14/161499/landingpagelatticeecp2m_sml.jpg)
LFE2M20SE-5FN256C
Manufacturer Part Number
LFE2M20SE-5FN256C
Description
FPGA - Field Programmable Gate Array 19K LUTs 140 I/O S-Ser SERDES DSP -5
Manufacturer
Lattice
Datasheet
1.LFE2-12SE-6FN256C.pdf
(389 pages)
Specifications of LFE2M20SE-5FN256C
Number Of Macrocells
19000
Maximum Operating Frequency
311 MHz
Number Of Programmable I/os
140
Data Ram Size
1246208
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2M20SE-5FN256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
LatticeECP2 Pin Information Summary, LFE2-20 and LFE2-35 (Cont.)
Available DDR-Interfaces per I/O
Bank
PCI Capable I/Os per Bank
1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1
DQSB + 8 DQs + 1 DM + Bank VREF1).
1
Pin Type
Bank0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
Bank8
Bank0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
Bank8
4-8
PQFP
208
19
18
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
fpBGA
256
32
17
0
0
1
0
2
1
1
1
0
0
0
0
0
0
0
0
LFE2-20
LatticeECP2/M Family Data Sheet
fpBGA
484
46
46
0
0
2
0
3
3
2
2
0
0
0
0
0
0
0
0
fpBGA
672
50
68
0
0
2
2
3
4
3
2
0
0
0
0
0
0
0
0
Pinout Information
fpBGA
484
46
46
0
0
2
0
3
3
1
2
0
0
0
0
0
0
0
0
LFE2-35
fpBGA
672
54
68
0
0
3
2
3
4
3
3
0
0
0
0
0
0
0
0
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