LFE2M20SE-5FN256C Lattice, LFE2M20SE-5FN256C Datasheet - Page 15
![FPGA - Field Programmable Gate Array 19K LUTs 140 I/O S-Ser SERDES DSP -5](/photos/16/14/161499/landingpagelatticeecp2m_sml.jpg)
LFE2M20SE-5FN256C
Manufacturer Part Number
LFE2M20SE-5FN256C
Description
FPGA - Field Programmable Gate Array 19K LUTs 140 I/O S-Ser SERDES DSP -5
Manufacturer
Lattice
Datasheet
1.LFE2-12SE-6FN256C.pdf
(389 pages)
Specifications of LFE2M20SE-5FN256C
Number Of Macrocells
19000
Maximum Operating Frequency
311 MHz
Number Of Programmable I/os
140
Data Ram Size
1246208
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2M20SE-5FN256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Figure 2-10. Primary Clock Sources for ECP2-50
DLL Input
PLL Input
PLL Input
Clock
Clock
Input
Input
Note: This diagram shows sources for the ECP2-50 device. Smaller LatticeECP2 devices have fewer SPLLs. All LatticeECP2M device
have six SPLLs.
GPLL
SPLL
DLL
CLK
DIV
From Routing
to Eight Quadrant Clock Selection
Clock Input
Primary Clock Sources
Clock Input
Clock Input
2-12
From Routing
Clock Input
LatticeECP2/M Family Data Sheet
GPLL
SPLL
CLK
DLL
DIV
Architecture
PLL Input
Clock
Input
Clock
Input
DLL Input
PLL Input
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