LFE2M20SE-5FN256C Lattice, LFE2M20SE-5FN256C Datasheet - Page 223
![FPGA - Field Programmable Gate Array 19K LUTs 140 I/O S-Ser SERDES DSP -5](/photos/16/14/161499/landingpagelatticeecp2m_sml.jpg)
LFE2M20SE-5FN256C
Manufacturer Part Number
LFE2M20SE-5FN256C
Description
FPGA - Field Programmable Gate Array 19K LUTs 140 I/O S-Ser SERDES DSP -5
Manufacturer
Lattice
Datasheet
1.LFE2-12SE-6FN256C.pdf
(389 pages)
Specifications of LFE2M20SE-5FN256C
Number Of Macrocells
19000
Maximum Operating Frequency
311 MHz
Number Of Programmable I/os
140
Data Ram Size
1246208
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2M20SE-5FN256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.)
Lattice Semiconductor
Ball Number
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
GND
GND
GND
GND
M26
M24
M25
M23
M27
M28
M29
M30
P25
P23
P27
P28
N24
N26
N23
N25
P29
P30
N29
N30
K24
K26
K23
K25
K27
L26
L24
L25
L23
L27
L28
L29
L30
Ball/Pad Function
GNDIO2
GNDIO2
GNDIO2
GNDIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
PR51B
PR51A
PR50B
PR50A
PR39B
PR39A
PR38B
PR38A
PR37B
PR37A
PR36B
PR36A
PR35B
PR35A
PR34B
PR34A
PR33B
PR33A
PR32B
PR32A
PR31B
PR31A
PR30B
PR30A
PR29B
PR29A
PR28B
PR28A
PR27B
PR27A
PR26B
PR26A
PR25B
LFE2-70E/SE
Bank
4-120
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
-
-
-
-
RUM0_SPLLC_FB_A/RDQ37
RUM0_SPLLT_FB_A/RDQ37
RUM0_SPLLC_IN_A/RDQ37
RUM0_SPLLT_IN_A/RDQ37
LatticeECP2/M Family Data Sheet
Dual Function
RDQS37
RDQS29
RDQ54
RDQ54
RDQ54
RDQ54
RDQ37
RDQ37
RDQ37
RDQ37
RDQ37
RDQ37
RDQ37
RDQ37
RDQ37
RDQ29
RDQ29
RDQ29
RDQ29
RDQ29
RDQ29
RDQ29
RDQ29
RDQ29
RDQ29
RDQ29
RDQ29
RDQ29
RDQ29
Pinout Information
Differential
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
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