LFXP2-5E-5TN144I Lattice, LFXP2-5E-5TN144I Datasheet - Page 229

• Manufacturer Part Number: LFXP2-5E-5TN144I
• Description: FPGA - Field Programmable Gate Array 5K LUTs 100 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-5E-5TN144I

• Number Of Macrocells: 5000
• Number Of Programmable I/os: 100
• Data Ram Size: 169984
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: TQFP-144
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 169984
• Number Of I /o: 100
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 11-29. IDDRFXA Symbol
Table 11-7 lists the port names and descriptions for the IDDRFXA primitive.
Table 11-7. IDDRFXA Port Names
Figure 11-31 shows the LatticeXP2 Input Register Block configured in the IDDRXFXA mode. CLK1 used to register
the DDR registers and the first set of synchronization registers. CLK2 is used by the third stage of registers and
should be clocked by the FPGA clock. These clock transfer registers are shared with the output register block.
Figure 11-30. Input Register Block configured as IDDRFXA
Figure 11-31 shows the timing waveform when using the IDDRFXA module.
DATA
D
CLK1
CLK2
CE
RST
QA
QB
Port Name
I/O
O
O
I
I
I
I
I
DDR Registers
B
A
DDR data
This clock can be connected to the ECLK or the FPGA clock
This clock should be connected to the FPGA clock
Clock Enable signal
Reset to the DDR register
Data at the positive edge of the clock
Data at the negative edge of the clock
D
CLK1
CLK2
CE
RST
C
Edge Clock
IDDRFXA
11-25
IDDRFXA
CLK1
Synchronization
QA
QB
Registers
Description
E
LatticeXP2 High-Speed I/O Interface
D
FPGA Clock
CLK2
Clock Transfer
Registers
H
I
QB
QA