LFXP2-5E-5TN144I Lattice, LFXP2-5E-5TN144I Datasheet - Page 206

• Manufacturer Part Number: LFXP2-5E-5TN144I
• Description: FPGA - Field Programmable Gate Array 5K LUTs 100 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-5E-5TN144I

• Number Of Macrocells: 5000
• Number Of Programmable I/os: 100
• Data Ram Size: 169984
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: TQFP-144
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 169984
• Number Of I /o: 100
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 11-1. Typical DDR SDRAM Interface
Figure 11-2. Typical DDR2 SDRAM Interface
The following two figures show the DQ and DQS relationship for memory read and write interfaces.
Figure 11-3. DQ-DQS During READ
(DDR Memory Controller)
(DDR Memory Controller)
(at REG)
(at REG)
(at PIN)
(at PIN)
DQS
DQS
DQ
DQ
FPGA
FPGA
DQS, DQS#
COMMAND
COMMAND
ADDRESS
CONTROL
CLK/CLKN
CLK/CLKN
ADDRESS
CONTROL
DQ<7:0>
DQ<7:0>
DQS
DM
DM
Preamble
CLKP/CLKN
COMMAND
DQS, DQS#
CLKP/CLKN
COMMAND
ADDRESS
CONTROL
CONTROL
ADDRESS
REG and 90
DQS PIN to
Phase Shift
DQ<7:0>
DQ<7:0>
Degree
DQS
DM
DM
11-2
8
X
Y
Z
8
X
Y
Z
LatticeXP2 High-Speed I/O Interface
Postamble
DQ<7:0>
DQS
DM
ADDRESS
COMMAND
CONTROL
CLK/CLKN
DQ<7:0>
DQS, DQS#
DM
ADDRESS
COMMAND
CONTROL
CLK/CLKN
DDR Memory
DDR Memory