LFXP2-5E-5TN144I Lattice, LFXP2-5E-5TN144I Datasheet - Page 131
LFXP2-5E-5TN144I
Manufacturer Part Number
LFXP2-5E-5TN144I
Description
FPGA - Field Programmable Gate Array 5K LUTs 100 I/O Inst on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet
1.LFXP2-8E-5FTN256I.pdf
(341 pages)
Specifications of LFXP2-5E-5TN144I
Number Of Macrocells
5000
Number Of Programmable I/os
100
Data Ram Size
169984
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
TQFP-144
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
169984
Number Of I /o
100
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
-40°C ~ 100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-5E-5TN144I
Manufacturer:
TI
Quantity:
2 900
Company:
Part Number:
LFXP2-5E-5TN144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Dynamic Phase and Dynamic Duty
This mode allows designers to use both DDPHASE[3:0] and DDUTY[3:0] ports to input dynamic values.
To use Dynamic Phase Adjustment with a fixed duty cycle other than a 50%, simply set the DDUTY[3:0] inputs to
the desired duty cycle value. Figure 9-7 illustrates an example circuit.
Example: Assume a design uses dynamic phase adjustment and a fixed duty cycle select and the desired duty
cycle in 3/16th of a period. The setup should be as shown in Figure 9-7.
Figure 9-7. Example of Dynamic Phase Adjustment with a Fixed Duty Cycle of 3/16th of a Period
Dynamic Phase Adjustment/Duty Cycle Select
Phase Adjustment settings are described in Table 9-5.
Table 9-5. Phase Adjustment Settings
DPHASE[3:0]
DPHASE[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
9-9
Phase (°)
DPHASE[3]
DPHASE[2]
DPHASE[1]
DPHASE[0]
DPAMODE
DDUTY[3]
DDUTY[2]
DDUTY[1]
DDUTY[0]
112.5
157.5
202.5
247.5
292.5
337.5
22.5
67.5
135
180
225
270
315
45
90
0
PLL
LatticeXP2 sysCLOCK PLL
Design and Usage Guide
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