LFXP2-5E-5TN144I Lattice, LFXP2-5E-5TN144I Datasheet - Page 190
LFXP2-5E-5TN144I
Manufacturer Part Number
LFXP2-5E-5TN144I
Description
FPGA - Field Programmable Gate Array 5K LUTs 100 I/O Inst on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet
1.LFXP2-8E-5FTN256I.pdf
(341 pages)
Specifications of LFXP2-5E-5TN144I
Number Of Macrocells
5000
Number Of Programmable I/os
100
Data Ram Size
169984
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
TQFP-144
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
169984
Number Of I /o
100
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
-40°C ~ 100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-5E-5TN144I
Manufacturer:
TI
Quantity:
2 900
Company:
Part Number:
LFXP2-5E-5TN144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Ports such as Out Clock (OutClock) and Out Clock Enable (OutClockEn) are not available in the hardware primi-
tive. These are generated by IPexpress when the user wants to enable the output registers in the IPexpress config-
uration.
The various ports and their definitions for memory are as per Table 10-16. The table lists the corresponding ports
for the module generated by IPexpress and for the primitive.
Table 10-16. PFU-based Distributed ROM Port Definitions
Users have the option to enable the output registers for Distributed ROM (Distributed_ROM). Figures 10-46 and
10-47 show the internal timing waveforms for the Distributed ROM with these options.
Figure 10-46. PFU Based ROM Timing Waveform – without Output Registers
Figure 10-47. PFU Based ROM Timing Waveform – with Output Registers
Generated Module
Port Name in
OutClockEn
OutClockEn
OutClock
Address
Address
Reset
OutClock
Address
Q
Reset
Q
Q
t
SUADDR_PFU
t
SUADDR_PFU
Invalid Data
Port Name in the PFU
Block Primitive
AD[3:0]
Add_0
DO
Add_0
—
—
—
Invalid Data
t
HADDR_PFU
t
HADDR_PFU
t
CORAM_PFU
10-40
Data_0
Add_1
Add_1
Out Clock Enable
Description
Out Clock
Data Out
Address
Reset
CORAM_PFU
LatticeXP2 Memory Usage Guide
Data_1
Add_2
Data_0
Add_2
Rising Clock Edge
Active State
Active High
Active High
Data_2
Data_1
—
—
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